From patchwork Mon Sep 23 08:22:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas KANDAGATLA X-Patchwork-Id: 2926461 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C74BA9F288 for ; Mon, 23 Sep 2013 08:25:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8F34620127 for ; Mon, 23 Sep 2013 08:25:25 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1BE1C2010F for ; Mon, 23 Sep 2013 08:25:24 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO1S6-0006aS-5m; Mon, 23 Sep 2013 08:25:06 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO1Ry-00079Y-G0; Mon, 23 Sep 2013 08:24:58 +0000 Received: from eu1sys200aog125.obsmtp.com ([207.126.144.159]) by merlin.infradead.org with smtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VO1Ru-00076l-Pp for linux-arm-kernel@lists.infradead.org; Mon, 23 Sep 2013 08:24:56 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob125.postini.com ([207.126.147.11]) with SMTP ID DSNKUj/6sQtxk9zqBFtKS0+QoNz2Y94Z3JvO@postini.com; Mon, 23 Sep 2013 08:24:54 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E41F69A; Mon, 23 Sep 2013 08:24:11 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6C9571D07; Mon, 23 Sep 2013 08:24:10 +0000 (GMT) Received: from localhost (king.bri.st.com [10.65.51.59]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BMW78549 (AUTH srinivak); Mon, 23 Sep 2013 10:24:08 +0200 From: Srinivas KANDAGATLA To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: STi: Add cpu hotplug support Date: Mon, 23 Sep 2013 09:22:10 +0100 Message-Id: <1379924530-26319-1-git-send-email-srinivas.kandagatla@st.com> X-Mailer: git-send-email 1.7.6.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130923_042455_067668_78A1E7F9 X-CRM114-Status: GOOD ( 18.13 ) X-Spam-Score: -4.2 (----) Cc: Stuart Menefy , Srinivas Kandagatla , Russell King , kernel@stlinux.com, lee.jones@linaro.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds cpu hotplug support to STi series SoCs. This code is cloned from arch/arm/mach-realview/hotplug.c. STiH415 and STiH416 SOCs do not have power control lines wired up to each core, so all we can do is to put the core into WFI for hotplug support. Tested on B2000 and B2020 boards with STiH415 and STiH416. Signed-off-by: Srinivas Kandagatla --- arch/arm/mach-sti/platsmp.c | 100 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 100 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index dce50d9..cdf9e2c 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "smp.h" @@ -110,8 +111,107 @@ void __init sti_smp_prepare_cpus(unsigned int max_cpus) } } +#ifdef CONFIG_HOTPLUG_CPU + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_louis(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " dsb\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + " mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + dsb(); + wfi(); + + if (pen_release == cpu_logical_map(cpu)) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void __ref sti_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} + +#endif /* CONFIG_HOTPLUG_CPU */ + struct smp_operations __initdata sti_smp_ops = { .smp_prepare_cpus = sti_smp_prepare_cpus, .smp_secondary_init = sti_secondary_init, .smp_boot_secondary = sti_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = sti_cpu_die, +#endif };