| Message ID | 1380057120-27108-1-git-send-email-dinguyen@altera.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/24/2013 03:11 PM, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > The STMMAC Ethernet controller in SOCFPGA requires setting a register for > the phy-mode that is outside of the ethernet IP. This register resides in > the System Manager block. So we define a new DTS binding > "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be > used to set the correct register bit. > diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt > +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to > + set the appropriate register bits for the phy-mode in the System Manager. > + The value should be: > + -Ethernet Controller 1 (gmac0) = 0x3 > + -Ethernet Controller 2 (gmac1) = 0xC Wouldn't you need a phandle to the sysmgr node so that the driver could be located, and a register number within its register block too? Or, does sysmgr know which register to poke? If so, couldn't the API take just a device index rather than a bitmask instead, and calculate the mask itself?
Hi Stephen, On 9/26/13 6:21 PM, Stephen Warren wrote: > On 09/24/2013 03:11 PM, dinguyen@altera.com wrote: >> From: Dinh Nguyen <dinguyen@altera.com> >> >> The STMMAC Ethernet controller in SOCFPGA requires setting a register for >> the phy-mode that is outside of the ethernet IP. This register resides in >> the System Manager block. So we define a new DTS binding >> "altr,sysmgr-phy-mask". This binding's property is a bitmask that can be >> used to set the correct register bit. >> diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt >> +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to >> + set the appropriate register bits for the phy-mode in the System Manager. >> + The value should be: >> + -Ethernet Controller 1 (gmac0) = 0x3 >> + -Ethernet Controller 2 (gmac1) = 0xC > Wouldn't you need a phandle to the sysmgr node so that the driver could > be located, and a register number within its register block too? Or, > does sysmgr know which register to poke? If so, couldn't the API take > just a device index rather than a bitmask instead, and calculate the > mask itself? The function that pokes this register is a platform specific init function call from the driver, so the function knows which register in the the sysmgr to poke. The first byte of the register has controls for both ethernet controllers. I thought it would be better to use a mask to be used to differentiate between each controller. Thanks, Dinh
diff --git a/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt new file mode 100644 index 0000000..f0fa56a --- /dev/null +++ b/Documentation/devicetree/bindings/net/stmmac-altr-socfpga.txt @@ -0,0 +1,43 @@ +* Altera SOCFPGA specific extensions to the STMicroelectronics + 10/100/1000 Ethernet driver (GMAC) + +This file documents an additional property that is required for the Altera +SOCFPGA implementation of the STMMAC Ethernet driver. Please refer to the core +properties of the STMMAC driver as documented in stmmac.txt. + +Required Properties: + +* compatible: should be + - "altr,socfpga-stmmac": for controllers with Altera SOCFPGA specific + extensions. + +* altr,sysmgr-phy-mask: This property contains the bitmask that is needed to + set the appropriate register bits for the phy-mode in the System Manager. + The value should be: + -Ethernet Controller 1 (gmac0) = 0x3 + -Ethernet Controller 2 (gmac1) = 0xC + +Example: + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq""; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "gmii"; + + /* PHY Skew settings */ + rxd0-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + + altr,sysmgr-phy-mask = <0x3>; + status = "okay"; + }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index bfed066..44db0e6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -95,3 +95,22 @@ }; }; }; + +&gmac1 { + phy-mode = "rgmii"; + snps,phy-addr = <0xffffffff>; /* probe for phy addr */ + + rxd0-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + + altr,sysmgr-phy-mask = <0xC>; + status = "okay"; +}; +