@@ -1973,8 +1973,33 @@ vip3_gclk_mux: vip3_gclk_mux@4a009030 {
reg = <0x4a009030 0x4>;
};
+optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a00821c 0x4>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+};
+
+optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <9>;
+};
+
+optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x4a0093b0 0x4>;
+ ti,bit-shift = <10>;
+};
+
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
-};
\ No newline at end of file
+};