| Message ID | 1380209654-25458-1-git-send-email-pdeschrijver@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/26/2013 09:34 AM, Peter De Schrijver wrote: > Add spread spectrum control for PLLE in Tegra114. It would be useful to have some description of the end-user-visible benefit of this change; why is it useful? Tested-by: Stephen Warren <swarren@nvidia.com> (on Beaver and Harmony, a PCIe Ethernet NIC passes traffic just fine).
On Tue, Oct 01, 2013 at 09:56:26PM +0200, Stephen Warren wrote: > On 09/26/2013 09:34 AM, Peter De Schrijver wrote: > > Add spread spectrum control for PLLE in Tegra114. > > It would be useful to have some description of the end-user-visible > benefit of this change; why is it useful? spread spectrum clocking is a technique to reduce EMI caused by the clock signal by modulating the frequency with a low frequency signal. This should reduce interference with eg. Wifi or cellular modems on the same board. Cheers, Peter.
On 10/03/2013 04:52 AM, Peter De Schrijver wrote: > On Tue, Oct 01, 2013 at 09:56:26PM +0200, Stephen Warren wrote: >> On 09/26/2013 09:34 AM, Peter De Schrijver wrote: >>> Add spread spectrum control for PLLE in Tegra114. >> >> It would be useful to have some description of the end-user-visible >> benefit of this change; why is it useful? > > spread spectrum clocking is a technique to reduce EMI caused by the clock > signal by modulating the frequency with a low frequency signal. This should > reduce interference with eg. Wifi or cellular modems on the same board. Great. The intent of my request was for that information to be included in the patch description.
On Thu, Oct 03, 2013 at 05:23:55PM +0200, Stephen Warren wrote: > On 10/03/2013 04:52 AM, Peter De Schrijver wrote: > > On Tue, Oct 01, 2013 at 09:56:26PM +0200, Stephen Warren wrote: > >> On 09/26/2013 09:34 AM, Peter De Schrijver wrote: > >>> Add spread spectrum control for PLLE in Tegra114. > >> > >> It would be useful to have some description of the end-user-visible > >> benefit of this change; why is it useful? > > > > spread spectrum clocking is a technique to reduce EMI caused by the clock > > signal by modulating the frequency with a low frequency signal. This should > > reduce interference with eg. Wifi or cellular modems on the same board. > > Great. The intent of my request was for that information to be included > in the patch description. > Mike, Do you want a version 2 for this? Cheers, Peter.
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 87f0533..f0577e3 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -77,7 +77,23 @@ #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) #define PLLE_SS_CTRL 0x68 -#define PLLE_SS_DISABLE (7 << 10) +#define PLLE_SS_CNTL_BYPASS_SS BIT(10) +#define PLLE_SS_CNTL_INTERP_RESET BIT(11) +#define PLLE_SS_CNTL_SSC_BYP BIT(12) +#define PLLE_SS_CNTL_CENTER BIT(14) +#define PLLE_SS_CNTL_INVERT BIT(15) +#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ + PLLE_SS_CNTL_SSC_BYP) +#define PLLE_SS_MAX_MASK 0x1ff +#define PLLE_SS_MAX_VAL 0x25 +#define PLLE_SS_INC_MASK (0xff << 16) +#define PLLE_SS_INC_VAL (0x1 << 16) +#define PLLE_SS_INCINTRV_MASK (0x3f << 24) +#define PLLE_SS_INCINTRV_VAL (0x20 << 24) +#define PLLE_SS_COEFFICIENTS_MASK \ + (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) +#define PLLE_SS_COEFFICIENTS_VAL \ + (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) #define PLLE_AUX_PLLP_SEL BIT(2) #define PLLE_AUX_ENABLE_SWCTL BIT(4) @@ -1286,6 +1302,18 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) if (ret < 0) goto out; + val = pll_readl(PLLE_SS_CTRL, pll); + val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); + val &= ~PLLE_SS_COEFFICIENTS_MASK; + val |= PLLE_SS_COEFFICIENTS_VAL; + pll_writel(val, PLLE_SS_CTRL, pll); + val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); + pll_writel(val, PLLE_SS_CTRL, pll); + udelay(1); + val &= ~PLLE_SS_CNTL_INTERP_RESET; + pll_writel(val, PLLE_SS_CTRL, pll); + udelay(1); + /* TODO: enable hw control of xusb brick pll */ out:
Add spread spectrum control for PLLE in Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 30 +++++++++++++++++++++++++++++- 1 files changed, 29 insertions(+), 1 deletions(-)