From patchwork Mon Sep 30 06:13:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiubo Li X-Patchwork-Id: 2962651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5917D9F95C for ; Mon, 30 Sep 2013 06:53:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1CEEB2024F for ; Mon, 30 Sep 2013 06:53:19 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 786052021E for ; Mon, 30 Sep 2013 06:53:17 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQWr4-0007dO-Jh; Mon, 30 Sep 2013 06:21:15 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQWqj-0001mm-MO; Mon, 30 Sep 2013 06:20:53 +0000 Received: from mail-db8lp0189.outbound.messaging.microsoft.com ([213.199.154.189] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQWqP-0001jO-7L for linux-arm-kernel@lists.infradead.org; Mon, 30 Sep 2013 06:20:37 +0000 Received: from mail210-db8-R.bigfish.com (10.174.8.244) by DB8EHSOBE042.bigfish.com (10.174.4.105) with Microsoft SMTP Server id 14.1.225.22; Mon, 30 Sep 2013 06:20:01 +0000 Received: from mail210-db8 (localhost [127.0.0.1]) by mail210-db8-R.bigfish.com (Postfix) with ESMTP id 60B8238008D; Mon, 30 Sep 2013 06:20:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 4 X-BigFish: VS4(z551bizc8kzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail210-db8 (localhost.localdomain [127.0.0.1]) by mail210-db8 (MessageSwitch) id 1380521991615847_18516; Mon, 30 Sep 2013 06:19:51 +0000 (UTC) Received: from DB8EHSMHS013.bigfish.com (unknown [10.174.8.231]) by mail210-db8.bigfish.com (Postfix) with ESMTP id 8CB9630027A; Mon, 30 Sep 2013 06:19:51 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS013.bigfish.com (10.174.4.23) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 30 Sep 2013 06:19:51 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 30 Sep 2013 06:19:49 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r8U6JXhr004271; Sun, 29 Sep 2013 23:19:43 -0700 From: Xiubo Li To: , Subject: [PATCHv5 1/4] pwm: Add Freescale FTM PWM driver support Date: Mon, 30 Sep 2013 14:13:28 +0800 Message-ID: <1380521611-2764-2-git-send-email-Li.Xiubo@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1380521611-2764-1-git-send-email-Li.Xiubo@freescale.com> References: <1380521611-2764-1-git-send-email-Li.Xiubo@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130930_022033_758374_69D26205 X-CRM114-Status: GOOD ( 23.82 ) X-Spam-Score: 1.5 (+) Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, linux@arm.linux.org.uk, ian.campbell@citrix.com, pawel.moll@arm.com, swarren@wwwdotorg.org, s.hauer@pengutronix.de, linux-doc@vger.kernel.org, Alison Wang , linux-kernel@vger.kernel.org, rob.herring@calxeda.com, Jingchang Lu , devicetree@vger.kernel.org, rob@landley.net, grant.likely@linaro.org, t.figa@samsung.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The FTM PWM device can be found on Vybrid VF610 Tower and Layerscape LS-1 SoCs. Signed-off-by: Xiubo Li Signed-off-by: Alison Wang Signed-off-by: Jingchang Lu Reviewed-by: Sascha Hauer --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-fsl-ftm.c | 442 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 453 insertions(+) create mode 100644 drivers/pwm/pwm-fsl-ftm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 75840b5..8144fb0 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -62,6 +62,16 @@ config PWM_BFIN To compile this driver as a module, choose M here: the module will be called pwm-bfin. +config PWM_FSL_FTM + tristate "Freescale FTM PWM support" + depends on OF + help + Generic FTM PWM framework driver for Freescale VF610 and + Layerscape LS-1 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-fsl-ftm. + config PWM_IMX tristate "i.MX PWM support" depends on ARCH_MXC diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 77a8c18..f383784 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o +obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c new file mode 100644 index 0000000..3bb6390 --- /dev/null +++ b/drivers/pwm/pwm-fsl-ftm.c @@ -0,0 +1,442 @@ +/* + * Freescale FTM PWM Driver + * + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FTM_SC 0x00 +#define FTMSC_CLK_MASK 0x03 +#define FTMSC_CLK_OFFSET 0x03 +#define FTMSC_CLKSYS (0x01 << 3) +#define FTMSC_CLKFIX (0x02 << 3) +#define FTMSC_CLKEXT (0x03 << 3) +#define FTMSC_PS_MASK 0x07 +#define FTMSC_PS_OFFSET 0x00 + +#define FTM_CNT 0x04 +#define FTM_MOD 0x08 + +#define FTM_CSC_BASE 0x0C +#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) +#define FTMCnSC_MSB BIT(5) +#define FTMCnSC_MSA BIT(4) +#define FTMCnSC_ELSB BIT(3) +#define FTMCnSC_ELSA BIT(2) + +#define FTM_CV_BASE 0x10 +#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) + +#define FTM_CNTIN 0x4C +#define FTM_STATUS 0x50 + +#define FTM_MODE 0x54 +#define FTMMODE_FTMEN BIT(0) +#define FTMMODE_INIT BIT(2) +#define FTMMODE_PWMSYNC BIT(3) + +#define FTM_SYNC 0x58 +#define FTM_OUTINIT 0x5C +#define FTM_OUTMASK 0x60 +#define FTM_COMBINE 0x64 +#define FTM_DEADTIME 0x68 +#define FTM_EXTTRIG 0x6C +#define FTM_POL 0x70 +#define FTM_FMS 0x74 +#define FTM_FILTER 0x78 +#define FTM_FLTCTRL 0x7C +#define FTM_QDCTRL 0x80 +#define FTM_CONF 0x84 +#define FTM_FLTPOL 0x88 +#define FTM_SYNCONF 0x8C +#define FTM_INVCTRL 0x90 +#define FTM_SWOCTRL 0x94 +#define FTM_PWMLOAD 0x98 + +#define FTM_CNTIN_VAL 0x00 +#define FTM_MAX_CHANNEL 8 + +enum { + FSL_COUNTER_CLK_SYS = 0, + FSL_COUNTER_CLK_FIX, + FSL_COUNTER_CLK_EXT, + FSL_COUNTER_CLK_MAX, +}; + +struct fsl_pwm_chip { + struct pwm_chip chip; + + struct clk *sys_clk; + struct clk *counter_clk; + unsigned int counter_clk_select; + unsigned int counter_clk_enable; + unsigned int clk_ps; + + void __iomem *base; +}; + +static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct fsl_pwm_chip, chip); +} + +static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + int ret; + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + ret = clk_prepare_enable(fpc->sys_clk); + if (ret) + return ret; + + return 0; +} + +static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + clk_disable_unprepare(fpc->sys_clk); +} + +static unsigned long fsl_rate_to_cycles(struct fsl_pwm_chip *fpc, + unsigned long time_ns) +{ + unsigned long long c; + unsigned long ps = 1 << fpc->clk_ps; + + if (fpc->counter_clk) + c = clk_get_rate(fpc->counter_clk); + else + c = clk_get_rate(fpc->sys_clk); + + c = c * time_ns; + do_div(c, 1000000000UL); + do_div(c, ps); + + return (unsigned long)c; +} + +static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + unsigned long period_cycles, duty_cycles; + unsigned long cntin = FTM_CNTIN_VAL; + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + period_cycles = fsl_rate_to_cycles(fpc, period_ns); + if (period_cycles > 0xFFFF) { + dev_err(chip->dev, "required PWM period cycles(%lu) overflow " + "16-bits counter!\n", period_cycles); + return -EINVAL; + } + + duty_cycles = fsl_rate_to_cycles(fpc, duty_ns); + if (duty_cycles >= 0xFFFF) { + dev_err(chip->dev, "required PWM duty cycles(%lu) overflow " + "16-bits counter!\n", duty_cycles); + return -EINVAL; + } + + writel(FTMCnSC_MSB | FTMCnSC_ELSB, fpc->base + FTM_CSC(pwm->hwpwm)); + + writel(0xF0, fpc->base + FTM_OUTMASK); + writel(0x0F, fpc->base + FTM_OUTINIT); + writel(FTM_CNTIN_VAL, fpc->base + FTM_CNTIN); + + writel(period_cycles + cntin - 1, fpc->base + FTM_MOD); + writel(duty_cycles + cntin, fpc->base + FTM_CV(pwm->hwpwm)); + + return 0; +} + +static int fsl_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + unsigned long reg; + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + reg = readl(fpc->base + FTM_POL); + if (polarity == PWM_POLARITY_INVERSED) + reg |= BIT(pwm->hwpwm); + else + reg &= ~BIT(pwm->hwpwm); + writel(reg, fpc->base + FTM_POL); + + return 0; +} + +static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) +{ + int ret; + unsigned long reg; + + if (fpc->counter_clk_enable++) + return 0; + + ret = clk_prepare_enable(fpc->counter_clk); + if (ret) + return ret; + + reg = readl(fpc->base + FTM_SC); + reg &= ~((FTMSC_CLK_MASK << FTMSC_CLK_OFFSET) | + (FTMSC_PS_MASK << FTMSC_PS_OFFSET)); + /* select counter clock source */ + switch (fpc->counter_clk_select) { + case FSL_COUNTER_CLK_SYS: + reg |= FTMSC_CLKSYS; + break; + case FSL_COUNTER_CLK_FIX: + reg |= FTMSC_CLKFIX; + break; + case FSL_COUNTER_CLK_EXT: + reg |= FTMSC_CLKEXT; + break; + default: + break; + } + reg |= fpc->clk_ps; + writel(reg, fpc->base + FTM_SC); + + return 0; +} + +static int fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) +{ + unsigned long reg; + + if (--fpc->counter_clk_enable) + return 0; + + writel(0xFF, fpc->base + FTM_OUTMASK); + reg = readl(fpc->base + FTM_SC); + reg &= ~(FTMSC_CLK_MASK << FTMSC_CLK_OFFSET); + writel(reg, fpc->base + FTM_SC); + + clk_disable_unprepare(fpc->counter_clk); + + return 0; +} + +static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + fsl_counter_clock_enable(fpc); + + return 0; +} + +static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc; + + fpc = to_fsl_chip(chip); + + fsl_counter_clock_disable(fpc); +} + +static const struct pwm_ops fsl_pwm_ops = { + .request = fsl_pwm_request, + .free = fsl_pwm_free, + .config = fsl_pwm_config, + .set_polarity = fsl_pwm_set_polarity, + .enable = fsl_pwm_enable, + .disable = fsl_pwm_disable, + .owner = THIS_MODULE, +}; + +static int fsl_pwm_calculate_ps(struct fsl_pwm_chip *fpc) +{ + unsigned long long sys_rate, counter_rate, ratio; + + sys_rate = clk_get_rate(fpc->sys_clk); + if (!sys_rate) + return -EINVAL; + + counter_rate = clk_get_rate(fpc->counter_clk); + if (!counter_rate && fpc->counter_clk_select != FSL_COUNTER_CLK_SYS) { + dev_warn(fpc->chip.dev, + "the counter source clock is a dummy clock, " + "so select the system clock as default!\n"); + } + + if (!counter_rate) { + fpc->counter_clk = NULL; + fpc->counter_clk_select = FSL_COUNTER_CLK_SYS; + fpc->clk_ps = 7; + } + + switch (fpc->counter_clk_select) { + case FSL_COUNTER_CLK_FIX: + ratio = 2 * counter_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + case FSL_COUNTER_CLK_EXT: + ratio = 4 * counter_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + case FSL_COUNTER_CLK_SYS: + default: + break; + } + + return 0; +} + +static int fsl_pwm_parse_clk_ps(struct fsl_pwm_chip *fpc) +{ + const char *cname; + int ret, index; + struct device_node *np = fpc->chip.dev->of_node; + + ret = of_property_read_string_index(np, "fsl,pwm-counter-clk", 0, + &cname); + if (ret < 0) { + dev_err(fpc->chip.dev, + "failed to get \"fsl,pwm-counter-clk\": %d\n", + ret); + return ret; + } + + index = of_property_match_string(np, "clock-names", cname); + if (index < 0) + return index; + if (index >= FSL_COUNTER_CLK_MAX) + return -EINVAL; + fpc->counter_clk_select = index; + + fpc->sys_clk = devm_clk_get(fpc->chip.dev, "ftm0"); + if (IS_ERR(fpc->sys_clk)) { + ret = PTR_ERR(fpc->sys_clk); + dev_err(fpc->chip.dev, + "failed to get \"ftm0\" clock %d\n", ret); + return ret; + } + + switch (fpc->counter_clk_select) { + case FSL_COUNTER_CLK_SYS: + fpc->counter_clk = NULL; + break; + case FSL_COUNTER_CLK_FIX: + fpc->counter_clk = devm_clk_get(fpc->chip.dev, "ftm0_fix_sel"); + if (IS_ERR(fpc->counter_clk)) { + ret = PTR_ERR(fpc->counter_clk); + dev_err(fpc->chip.dev, + "failed to get \"ftm0_fix_sel\" " + "clock %d\n", ret); + return ret; + } + break; + case FSL_COUNTER_CLK_EXT: + fpc->counter_clk = devm_clk_get(fpc->chip.dev, "ftm0_ext_sel"); + if (IS_ERR(fpc->counter_clk)) { + ret = PTR_ERR(fpc->counter_clk); + dev_err(fpc->chip.dev, + "failed to get \"ftm0_ext_sel\" " + "clock %d\n", ret); + return ret; + } + break; + default: + break; + } + + return fsl_pwm_calculate_ps(fpc); +} + +static int fsl_pwm_probe(struct platform_device *pdev) +{ + int ret = 0; + struct fsl_pwm_chip *fpc; + struct resource *res; + + fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); + if (!fpc) + return -ENOMEM; + + fpc->chip.dev = &pdev->dev; + fpc->counter_clk_enable = 0; + + ret = fsl_pwm_parse_clk_ps(fpc); + if (ret < 0) + return ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + fpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fpc->base)) { + ret = PTR_ERR(fpc->base); + return ret; + } + + fpc->chip.ops = &fsl_pwm_ops; + fpc->chip.of_xlate = of_pwm_xlate_with_flags; + fpc->chip.of_pwm_n_cells = 3; + fpc->chip.base = -1; + fpc->chip.npwm = FTM_MAX_CHANNEL; + ret = pwmchip_add(&fpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, fpc); + + return 0; +} + +static int fsl_pwm_remove(struct platform_device *pdev) +{ + struct fsl_pwm_chip *fpc; + + fpc = platform_get_drvdata(pdev); + + return pwmchip_remove(&fpc->chip); +} + +static const struct of_device_id fsl_pwm_dt_ids[] = { + { .compatible = "fsl,vf610-ftm-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); + +static struct platform_driver fsl_pwm_driver = { + .driver = { + .name = "fsl-ftm-pwm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(fsl_pwm_dt_ids), + }, + .probe = fsl_pwm_probe, + .remove = fsl_pwm_remove, +}; +module_platform_driver(fsl_pwm_driver); + +MODULE_DESCRIPTION("Freescale FTM PWM Driver"); +MODULE_AUTHOR("Xiubo Li "); +MODULE_LICENSE("GPL");