From patchwork Tue Oct 1 10:57:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 2969451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 92AEBBFF0B for ; Tue, 1 Oct 2013 10:58:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4E35E203DB for ; Tue, 1 Oct 2013 10:58:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E18F8203DA for ; Tue, 1 Oct 2013 10:58:02 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQxeP-0002N8-Qi; Tue, 01 Oct 2013 10:57:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQxeN-0005NS-ED; Tue, 01 Oct 2013 10:57:55 +0000 Received: from mail-ee0-f43.google.com ([74.125.83.43]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VQxeK-0005Mv-8F for linux-arm-kernel@lists.infradead.org; Tue, 01 Oct 2013 10:57:53 +0000 Received: by mail-ee0-f43.google.com with SMTP id e52so3339580eek.16 for ; Tue, 01 Oct 2013 03:57:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vkbW82Knv0a1NBVr9CF8RIEYSdi8aiyM0O3ERUDOvbw=; b=W6bhSbikCqCFMo/nsKWmTkRI3hpZxIK42Mo687dKaqH2TIK/+R7XrLZI1z6HmhgHAo DG3kepTU8sJuq5KBfrAd5b2NGW4yRE3i2d9EstmK1ADxcFfFF2X2h8o3m37VnT1QXlRI HGbwAiOtlemdIZZdAcMDBm/C3N3soIFlh7jzkm5ZONN+qTXA5v+17r2xEmLCYFTIKlKZ 5dox06j9HfoHXhwO8L1LnhVRHrYmwh7ApJ1qXTKPIzoM+iuX5AHanqZ69SldlrxfskN2 XwLFz7UHOQZ3J/aKLnmr/SzG2djIUKKkv8ahsbaGN9ovxhtqjYipQTSUP54JAGF+4Kiq /GMA== X-Gm-Message-State: ALoCoQkBPuLU0y7ZpEEvP6HwXLlRF0kfKmUPPP2ocVM0MRjB2sZrIpxcQnFWtAmghAPnSB4vih95 X-Received: by 10.14.246.11 with SMTP id p11mr45710060eer.9.1380625049185; Tue, 01 Oct 2013 03:57:29 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id z12sm11891131eev.6.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 01 Oct 2013 03:57:28 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll Subject: [PATCH] RFT: ARM: gemini: convert to GENERIC_CLOCKEVENTS Date: Tue, 1 Oct 2013 12:57:20 +0200 Message-Id: <1380625040-25912-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131001_065752_537851_0341DACA X-CRM114-Status: GOOD ( 18.70 ) X-Spam-Score: -2.6 (--) Cc: Linus Walleij , arm@kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This converts the gemini machine to use generic clockevents by rewriting the timer driver. Cc: arm@kernel.org Cc: Hans Ulli Kroll Signed-off-by: Linus Walleij --- This is flagged as Request for Testing (RFT) as I have no Gemini platform. If I do not get help with testing this, the next step will be a patch series to delete the platform. --- arch/arm/Kconfig | 3 +- arch/arm/mach-gemini/time.c | 97 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 91 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1ad6fb6..1a903e6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -386,8 +386,9 @@ config ARCH_CLPS711X config ARCH_GEMINI bool "Cortina Systems Gemini" select ARCH_REQUIRE_GPIOLIB - select ARCH_USES_GETTIMEOFFSET + select CLKSRC_MMIO select CPU_FA526 + select GENERIC_CLOCKEVENTS select NEED_MACH_GPIO_H help Support for the Cortina Systems Gemini family SoCs diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index 21dc5a8..0a63c4d 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include /* * Register definitions for the timers @@ -33,19 +35,89 @@ #define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_INT (1 << 8) +static unsigned int tick_rate; + +static int gemini_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + u32 cr; + + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* This may be overdoing it, feel free to test without this */ + cr &= ~TIMER_2_CR_ENABLE; + cr &= ~TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* Set next event */ + writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); + writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); + cr |= TIMER_2_CR_ENABLE; + cr |= TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + return 0; +} + +static void gemini_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ); + u32 cr; + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* Start the timer */ + writel(period, + TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); + writel(period, + TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + cr |= TIMER_2_CR_ENABLE; + cr |= TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + /* + * Disable also for oneshot: the set_next() call will + * arm the timer instead. + */ + cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + cr &= ~TIMER_2_CR_ENABLE; + cr &= ~TIMER_2_CR_INT; + writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; + default: + break; + } +} + +/* Use TIMER2 as clock event */ +static struct clock_event_device gemini_clockevent = { + .name = "TIMER2", + .rating = 300, /* Reasonably fast and accurate clock event */ + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = gemini_timer_set_next_event, + .set_mode = gemini_timer_set_mode, +}; + /* * IRQ handler for the timer */ static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) { - timer_tick(); + struct clock_event_device *evt = &gemini_clockevent; + evt->event_handler(evt); return IRQ_HANDLED; } static struct irqaction gemini_timer_irq = { .name = "Gemini Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .handler = gemini_timer_interrupt, }; @@ -54,9 +126,9 @@ static struct irqaction gemini_timer_irq = { */ void __init gemini_timer_init(void) { - unsigned int tick_rate, reg_v; + u32 reg_v; - reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); + reg_v = readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000; printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000); @@ -82,8 +154,17 @@ void __init gemini_timer_init(void) * Make irqs happen for the system timer */ setup_irq(IRQ_TIMER2, &gemini_timer_irq); - /* Start the timer */ - __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); - __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); - __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + + /* Enable and use TIMER1 as clock source */ + writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); + writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); + writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), + "TIMER1", tick_rate, 300, 32, + clocksource_mmio_readl_up)) + pr_err("timer: failed to initialize gemini clock source\n"); + + /* Configure and register the clockevent */ + clockevents_config_and_register(&gemini_clockevent, tick_rate, + 1, 0xffffffff); }