From patchwork Wed Oct 2 12:39:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerlando Falauto X-Patchwork-Id: 2974751 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8BC3CBFF0B for ; Wed, 2 Oct 2013 12:49:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED5BE20319 for ; Wed, 2 Oct 2013 12:49:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D9E9201BD for ; Wed, 2 Oct 2013 12:49:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLjE-00070v-Dc; Wed, 02 Oct 2013 12:40:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLig-0007Oq-BG; Wed, 02 Oct 2013 12:39:58 +0000 Received: from mail-de.keymile.com ([195.8.104.250]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRLid-0007Nz-3S for linux-arm-kernel@lists.infradead.org; Wed, 02 Oct 2013 12:39:55 +0000 Received: from [10.9.1.54] (port=54627 helo=mailrelay.de.keymile.net) by mail-de.keymile.com with esmtp (Exim 4.76) (envelope-from ) id 1VRLiF-0007ZJ-22; Wed, 02 Oct 2013 14:39:31 +0200 Received: from chber1-10555x.ch.keymile.net ([172.31.40.82]) by mailrelay.de.keymile.net (8.12.2/8.12.2) with ESMTP id r92Cb71W000225; Wed, 2 Oct 2013 14:37:07 +0200 (MEST) From: Gerlando Falauto To: linux-kernel@vger.kernel.org Subject: [PATCH] orion-gpio: enable IRQ_GC_MASK_CACHE_PER_TYPE Date: Wed, 2 Oct 2013 14:39:28 +0200 Message-Id: <1380717568-11517-1-git-send-email-gerlando.falauto@keymile.com> X-Mailer: git-send-email 1.8.0.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131002_083955_274147_C0EF97F7 X-CRM114-Status: UNSURE ( 7.54 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) Cc: Simon Guinot , Holger Brunck , Gerlando Falauto , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP enable handling of separate mask registers for Orion SoC GPIOs, fixing indeed the regression introduced by e59347a "arm: orion: Use generic irq chip". Reported-by: Joey Oravec Signed-off-by: Holger Brunck Signed-off-by: Gerlando Falauto Cc: linux-arm-kernel@lists.infradead.org Cc: Simon Guinot --- #Cc: # 3.0.x cfeaa93 genirq: Generic chip: Remove the local cur_regs() function #Cc: # 3.0.x 899f0e6 genirq: Generic chip: Add support for per chip type mask cache #Cc: # 3.0.x af80b0f genirq: Generic chip: Handle separate mask registers #Cc: # 3.0.x arch/arm/plat-orion/gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index ebc0934..0b9f7c3 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -583,7 +583,8 @@ void __init orion_gpio_init(struct device_node *np, ct->handler = handle_edge_irq; ct->chip.name = ochip->chip.label; - irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE | + IRQ_GC_MASK_CACHE_PER_TYPE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */