From patchwork Thu Oct 3 21:18:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 2986131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3DB89BFF0B for ; Thu, 3 Oct 2013 21:26:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71477202C3 for ; Thu, 3 Oct 2013 21:26:46 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DCF0201EA for ; Thu, 3 Oct 2013 21:26:45 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRqO0-0008Ll-V9; Thu, 03 Oct 2013 21:24:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRqJ4-0000yb-Pd; Thu, 03 Oct 2013 21:19:35 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VRqId-0000tO-81 for linux-arm-kernel@lists.infradead.org; Thu, 03 Oct 2013 21:19:08 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r93LIc6w026314; Thu, 3 Oct 2013 16:18:38 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r93LIcev008768; Thu, 3 Oct 2013 16:18:38 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Thu, 3 Oct 2013 16:18:38 -0500 Received: from ula0393909.am.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r93LI3Bo024025; Thu, 3 Oct 2013 16:18:38 -0500 From: Santosh Shilimkar To: Subject: [PATCH v3 6/6] ARM: mm: Change the order of TLB/cache maintenance operations. Date: Thu, 3 Oct 2013 17:18:00 -0400 Message-ID: <1380835081-12129-7-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380835081-12129-1-git-send-email-santosh.shilimkar@ti.com> References: <1380835081-12129-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131003_171907_433329_7CAB8E89 X-CRM114-Status: GOOD ( 13.68 ) X-Spam-Score: -7.6 (-------) Cc: nicolas.pitre@linaro.org, linux@arm.linux.org.uk, Catalin Marinas , Sricharan R , arm@kernel.org, Santosh Shilimkar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sricharan R As per the arm ARMv7 manual, the sequence of TLB maintenance operations after making changes to the translation table is to clean the dcache first, then invalidate the TLB. With the current sequence we see cache corruption when the flush_cache_all is called after tlb_flush_all. STR rx, [Translation table entry] ; write new entry to the translation table Clean cache line [Translation table entry] DSB ; ensures visibility of the data cleaned from the D Cache Invalidate TLB entry by MVA (and ASID if non-global) [page address] Invalidate BTC DSB ; ensure completion of the Invalidate TLB operation ISB ; ensure table changes visible to instruction fetch The issue is seen only with LPAE + THUMB BUILT KERNEL + 64BIT patching, which is little bit weird. Cc: Catalin Marinas Cc: Nicolas Pitre Cc: Russell King - ARM Linux Signed-off-by: Sricharan R Signed-off-by: Santosh Shilimkar Acked-by: Nicolas Pitre --- arch/arm/mm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 47c7497..49cba8a 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -1280,8 +1280,8 @@ static void __init devicemaps_init(const struct machine_desc *mdesc) * any write-allocated cache lines in the vector page are written * back. After this point, we can start to touch devices again. */ - local_flush_tlb_all(); flush_cache_all(); + local_flush_tlb_all(); } static void __init kmap_init(void)