From patchwork Fri Oct 4 13:27:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 2988721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A62C9F245 for ; Fri, 4 Oct 2013 13:27:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AEF9F203A8 for ; Fri, 4 Oct 2013 13:27:39 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48F79202AE for ; Fri, 4 Oct 2013 13:27:38 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VS5Pr-0000Bk-FX; Fri, 04 Oct 2013 13:27:35 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VS5Po-0003sP-PW; Fri, 04 Oct 2013 13:27:32 +0000 Received: from mail-ea0-f175.google.com ([209.85.215.175]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VS5Pl-0003rj-Kk for linux-arm-kernel@lists.infradead.org; Fri, 04 Oct 2013 13:27:30 +0000 Received: by mail-ea0-f175.google.com with SMTP id m14so1818415eaj.34 for ; Fri, 04 Oct 2013 06:27:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=UTTKI9BOhfVZv0/kSYyNLlCMYUwp8ESmd/bSUOAha7A=; b=fhS5VEyoixc+6oN8RTRcWR/MA116fbzfwvjAPjohhyIv+93CUlW7qnB87CB5tYcgRs zYKZLyojkDtWgI+gbXBsK+fzxJ5S6qM5zku7821D6jNUeN2bTlnuwgUBjiijcJxbfb7s X7tVxA+AEdTOja4oowM2Q64coqKwmEMCVQDfdnyJKw50OeEK7BZAYon1IdUQuAEdgYy/ Hl2PkSFAA5ScutJIV2JBLI0Upg5JmGhQlO1gy0bpaBDeSRFfyZDE6PsBMNYafyOVL8Ql d04knnUpZ1B/zJsrslPB3DWDoV6kIMgu7Gvg1WwQ12svE5kbU5vaqhz/Mq7mLT/br5Oh Rv+Q== X-Gm-Message-State: ALoCoQkLhVhvEg0MGBbIyyZPEUm7+K+NewrMB1gO0JUSUHGQNlXGFqi5Qsd0yKjUEl/0nOFleCNK X-Received: by 10.15.77.132 with SMTP id p4mr143084eey.95.1380893226497; Fri, 04 Oct 2013 06:27:06 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id a43sm28074564eep.9.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 04 Oct 2013 06:27:05 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: integrator: pass parent IRQ to the SIC Date: Fri, 4 Oct 2013 15:27:02 +0200 Message-Id: <1380893222-7716-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131004_092729_912138_0DFB4708 X-CRM114-Status: UNSURE ( 9.70 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The SIC is cascaded off the PIC, so specify this in the device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integratorcp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index ff1aea0..f0ab05f 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -48,8 +48,11 @@ valid-mask = <0x00000007>; }; + /* The SIC is cascaded off IRQ 26 on the PIC */ sic: sic@ca000000 { compatible = "arm,versatile-fpga-irq"; + interrupt-parent = <&pic>; + interrupts = <26>; #interrupt-cells = <1>; interrupt-controller; reg = <0xca000000 0x100>;