From patchwork Mon Oct 7 10:27:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 2995511 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BCC61BF924 for ; Mon, 7 Oct 2013 10:27:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D253E2018E for ; Mon, 7 Oct 2013 10:27:48 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7E8DB2018C for ; Mon, 7 Oct 2013 10:27:47 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VT82Q-0003vc-4u; Mon, 07 Oct 2013 10:27:42 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VT82N-0007mM-2A; Mon, 07 Oct 2013 10:27:39 +0000 Received: from mail-ea0-f169.google.com ([209.85.215.169]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VT82K-0007la-4A for linux-arm-kernel@lists.infradead.org; Mon, 07 Oct 2013 10:27:36 +0000 Received: by mail-ea0-f169.google.com with SMTP id k11so3166118eaj.28 for ; Mon, 07 Oct 2013 03:27:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=DVR+auhsMZWKjWa2xB4TQ2AW0QB4rJ2D9EXnCY8FECA=; b=TVrRWdKFHjrsIADOpm+dao+TQFhj+gfdYmMMTCME6+g+79XAvaxgyOp8BNuFaJljR5 nxlRxc9Yewjm8l0WF8KuBbttWhc4X8Bl/7jp2Ix/UVmnCdFhMzgX3C2qlGTGW69Jrsse l8t259d8W3NpqSiy1C0skjdl/xV4DR3WHe+p6OJgRXN76Xf8Z4SPKuk07iDH866m7Lqi EAVSqRT/Mz8jav3ERpCXd+F6ezD1YcTndruC2DtV9Hk1w4UXron0DhvLbmyaurGvRjzv IdtPLOKVYLVqkp3SaLfQnnqXBtBLxfBK4sEYjjt0soXMnwhxLXeySPu/Sr6rF+c7hT4b D8WQ== X-Gm-Message-State: ALoCoQkWFAhwzu42oBWuIGFv1c3mJbGzyZCIZkWsE03SQf8l5sa3YPV/+TB7uyhiPLxZfS1KI2/D X-Received: by 10.15.67.131 with SMTP id u3mr47714106eex.34.1381141631281; Mon, 07 Oct 2013 03:27:11 -0700 (PDT) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id v8sm61665308eeo.12.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 07 Oct 2013 03:27:10 -0700 (PDT) From: Taras Kondratiuk To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: OMAP4/highbank: Flush L2 cache before disabling Date: Mon, 7 Oct 2013 13:27:01 +0300 Message-Id: <1381141621-29001-1-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131007_062736_302433_9C8BC33A X-CRM114-Status: GOOD ( 12.74 ) X-Spam-Score: -2.6 (--) Cc: linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, Will Deacon , Rob Herring , Santosh Shilimkar , steve.mcintyre@linaro.org, linux-omap@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Kexec disables outer cache before jumping to reboot code, but it doesn't flush it explicitly. Flush is done implicitly inside of l2x0_disable(). But some SoC's override default .disable handler and don't flush cache. This may lead to a corrupted memory during Kexec reboot on these platforms. This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() handlers to make it consistent with default l2x0_disable(). Also it removes redundant outer_flush_all() call just before outer_disable(). Acked-by: Rob Herring Acked-by: Santosh Shilimkar Signed-off-by: Taras Kondratiuk Acked-by: Tony Lindgren --- Based on v3.12-rc3 RFC v2: https://patchwork.kernel.org/patch/2990231/ Make the fix specific to platforms that don't use l2x0_disable(). RFC v1: https://patchwork.kernel.org/patch/2974431/ --- Cc: Will Deacon Cc: Russell King Cc: Rob Herring Cc: Santosh Shilimkar Cc: linaro-kernel@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-omap@vger.kernel.org --- arch/arm/mach-highbank/highbank.c | 1 + arch/arm/mach-highbank/pm.c | 1 - arch/arm/mach-omap2/omap4-common.c | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index 8e63ccd..22e6f34 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -63,6 +63,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr) static void highbank_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ highbank_smc1(0x102, 0x0); } diff --git a/arch/arm/mach-highbank/pm.c b/arch/arm/mach-highbank/pm.c index 04eddb4..9a5b8a7 100644 --- a/arch/arm/mach-highbank/pm.c +++ b/arch/arm/mach-highbank/pm.c @@ -28,7 +28,6 @@ static int highbank_suspend_finish(unsigned long val) { - outer_flush_all(); outer_disable(); highbank_set_pwr_suspend(); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2840d1e..f6ccab61 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -163,6 +163,7 @@ void __iomem *omap4_get_l2cache_base(void) static void omap4_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ omap_smc1(0x102, 0x0); }