From patchwork Tue Oct 8 07:47:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 3001181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 60056BF924 for ; Tue, 8 Oct 2013 07:48:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3B3B3201E9 for ; Tue, 8 Oct 2013 07:48:30 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA4EE201E4 for ; Tue, 8 Oct 2013 07:48:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTS1n-0007ht-5L; Tue, 08 Oct 2013 07:48:23 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTS1k-0005Ez-Jc; Tue, 08 Oct 2013 07:48:20 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTS1h-0005D0-5x for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2013 07:48:18 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 08 Oct 2013 00:47:50 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 08 Oct 2013 00:43:44 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 08 Oct 2013 00:43:44 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Tue, 8 Oct 2013 00:47:51 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH] ARM: tegra: add clock properties for devices of Tegra124 Date: Tue, 8 Oct 2013 15:47:40 +0800 Message-ID: <1381218460-23123-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.4 X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131008_034817_371833_B96462C0 X-CRM114-Status: GOOD ( 10.65 ) X-Spam-Score: -2.1 (--) Cc: linux-tegra@vger.kernel.org, Peter De Schrijver , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo --- This patch was based on the series of Tegra124 clock driver and the basic support of Tegra124. It coulud be used to replace the "HACK" patch in the basic support of Tegra124 series. --- arch/arm/boot/dts/tegra124-venice2.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 2bfc7ab..5859ec2 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -17,4 +17,17 @@ pmc@7000e400 { nvidia,invert-interrupt; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 905f148..7862024 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,3 +1,4 @@ +#include #include #include "skeleton.dtsi" @@ -27,6 +28,13 @@ , , ; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; }; /* @@ -43,6 +51,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; }; serial@70006040 { @@ -51,6 +60,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; }; serial@70006200 { @@ -59,6 +69,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; }; serial@70006300 { @@ -67,6 +78,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; }; serial@70006400 { @@ -75,6 +87,7 @@ reg-shift = <2>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; }; rtc@7000e000 { @@ -82,11 +95,14 @@ reg = <0x7000e000 0x100>; interrupts = ; status = "disabled"; + clocks = <&tegra_car TEGRA124_CLK_RTC>; }; pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; cpus {