From patchwork Tue Oct 8 12:24:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 3003531 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0E22ABF924 for ; Tue, 8 Oct 2013 12:28:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B842201BF for ; Tue, 8 Oct 2013 12:28:27 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0303A201B9 for ; Tue, 8 Oct 2013 12:28:26 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTWNA-00056e-CE; Tue, 08 Oct 2013 12:26:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTWMZ-0006Mx-OT; Tue, 08 Oct 2013 12:26:07 +0000 Received: from mail-bk0-x229.google.com ([2a00:1450:4008:c01::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTWLb-0006EG-0c for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2013 12:25:15 +0000 Received: by mail-bk0-f41.google.com with SMTP id na10so3199158bkb.14 for ; Tue, 08 Oct 2013 05:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=adl0dM1esKixbmGnjZl++fdspn9mwv2bxvjp3xHuj64=; b=V9Q5cG+av744uSuS7xyUteF5N09OXNwjOmikQ23MdRkVT/uQFdT/0839o6VpmFn4zU r98AW1EI0xctnEgxFw9bVSLq82yQbXWnpcmfHCFzYVADikR8AXqKBi11caRchirTI0cA BP4H5lAWOxPAUyU//o08dgKB9j9O8RvsH2zVIIdv5Jytf33+QpWqBJcRBj8m0tvDZmE4 /WIUOth2/pqDB49EeYBSlgne9vCED/6Og4Ak2AV1aByaJAoT4aq3a+rZEaXS8IIgmDw5 CkPdW330DrcVuRUSXQ1WhTGN++qSHpKEWtivxb8oqI2+5nKP047fJG8Cmwi3iOGJJhiE Snxw== X-Received: by 10.204.121.201 with SMTP id i9mr1300006bkr.13.1381235084384; Tue, 08 Oct 2013 05:24:44 -0700 (PDT) Received: from topkick.lan (dslc-082-083-247-252.pools.arcor-ip.net. [82.83.247.252]) by mx.google.com with ESMTPSA id pn6sm20312819bkb.14.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Oct 2013 05:24:43 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Subject: [PATCH 3/8] ARM: l2x0: add Marvell Tauros3 compatible Date: Tue, 8 Oct 2013 14:24:28 +0200 Message-Id: <1381235073-17134-4-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1381235073-17134-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <1381235073-17134-1-git-send-email-sebastian.hesselbarth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131008_082507_357258_E6B9D22E X-CRM114-Status: GOOD ( 14.86 ) X-Spam-Score: -2.0 (--) Cc: Thomas Petazzoni , devicetree@vger.kernel.org, Jason Cooper , Arnd Bergmann , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This add a compatible for the Marvell Tauros3 cache controller which is compatible with l2x0 cache controllers. While updating the binding documentation, clean up the list of possible compatibles. Signed-off-by: Sebastian Hesselbarth --- Cc: Jason Cooper Cc: Thomas Petazzoni Cc: Arnd Bergmann Cc: devicetree@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/arm/l2cc.txt | 22 +++++++++++----------- arch/arm/mm/cache-l2x0.c | 1 + 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index c0c7626..a1d0cbd 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -7,20 +7,20 @@ The ARM L2 cache representation in the device tree should be done as follows: Required properties: - compatible : should be one of: - "arm,pl310-cache" - "arm,l220-cache" - "arm,l210-cache" - "marvell,aurora-system-cache": Marvell Controller designed to be + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" + "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an + offset needs to be added to the address before passing down to the L2 + cache controller + "marvell,aurora-system-cache": Marvell Controller designed to be compatible with the ARM one, with system cache mode (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - "marvell,"aurora-outer-cache: Marvell Controller designed to be - compatible with the ARM one with outer cache mode. - "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an - offset needs to be added to the address before passing down to the L2 - cache controller - "bcm,bcm11351-a2-pl310-cache": DEPRECATED by - "brcm,bcm11351-a2-pl310-cache" + "marvell,aurora-outer-cache": Marvell Controller designed to be + compatible with the ARM one with outer cache mode. + "marvell,tauros3-cache": Marvell Tauros3 cache controller. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 447da6f..90c776e 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -929,6 +929,7 @@ static const struct of_device_id l2x0_ids[] __initconst = { .data = (void *)&aurora_no_outer_data}, { .compatible = "marvell,aurora-outer-cache", .data = (void *)&aurora_with_outer_data}, + { .compatible = "marvell,tauros3-cache", .data = (void *)&l2x0_data }, { .compatible = "brcm,bcm11351-a2-pl310-cache", .data = (void *)&bcm_l2x0_data}, { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */