From patchwork Wed Oct 9 09:20:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 3007851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A884FBF924 for ; Wed, 9 Oct 2013 09:22:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 83C7F20134 for ; Wed, 9 Oct 2013 09:22:11 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1385620124 for ; Wed, 9 Oct 2013 09:22:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTpxG-0004Jy-Af; Wed, 09 Oct 2013 09:21:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTpx1-0004se-25; Wed, 09 Oct 2013 09:21:03 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VTpwm-0004oo-2O for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2013 09:20:50 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 09 Oct 2013 02:20:19 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 09 Oct 2013 02:20:24 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 09 Oct 2013 02:20:24 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.327.1; Wed, 9 Oct 2013 02:20:23 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH 1/7] clk: tegra124: add suspend/resume function for tegra_cpu_car_ops Date: Wed, 9 Oct 2013 17:20:05 +0800 Message-ID: <1381310411-11391-2-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1381310411-11391-1-git-send-email-josephl@nvidia.com> References: <1381310411-11391-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131009_052048_393510_599A1F95 X-CRM114-Status: GOOD ( 11.58 ) X-Spam-Score: -2.1 (--) Cc: linux-tegra@vger.kernel.org, Mike Turquette , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette Signed-off-by: Joseph Lo Acked-by: Stephen Warren --- drivers/clk/tegra/clk-tegra124.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index c1c9330..66eb1f8a 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -28,6 +28,7 @@ #include "clk.h" #include "clk-id.h" +#define CLK_SOURCE_CSITE 0x1d4 #define CLK_SOURCE_EMC 0x19c #define CLK_SOURCE_XUSB_SS_SRC 0x610 @@ -109,6 +110,12 @@ /* Tegra CPU clock and reset control regs */ #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 +#ifdef CONFIG_PM_SLEEP +static struct cpu_clk_suspend_context { + u32 clk_csite_src; +} tegra124_cpu_clk_sctx; +#endif + static void __iomem *clk_base; static void __iomem *pmc_base; @@ -1139,9 +1146,29 @@ static void tegra124_disable_cpu_clock(u32 cpu) /* flow controller would take care in the power sequence. */ } +#ifdef CONFIG_PM_SLEEP +static void tegra124_cpu_clock_suspend(void) +{ + /* switch coresite to clk_m, save off original source */ + tegra124_cpu_clk_sctx.clk_csite_src = + readl(clk_base + CLK_SOURCE_CSITE); + writel(3 << 30, clk_base + CLK_SOURCE_CSITE); +} + +static void tegra124_cpu_clock_resume(void) +{ + writel(tegra124_cpu_clk_sctx.clk_csite_src, + clk_base + CLK_SOURCE_CSITE); +} +#endif + static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { .wait_for_reset = tegra124_wait_cpu_in_reset, .disable_clock = tegra124_disable_cpu_clock, +#ifdef CONFIG_PM_SLEEP + .suspend = tegra124_cpu_clock_suspend, + .resume = tegra124_cpu_clock_resume, +#endif }; static const struct of_device_id pmc_match[] __initconst = {