From patchwork Tue Oct 15 04:55:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 3041741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1975A9F2B7 for ; Tue, 15 Oct 2013 04:55:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17AA82018E for ; Tue, 15 Oct 2013 04:55:24 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E30D32017B for ; Tue, 15 Oct 2013 04:55:22 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VVwf4-0000cn-HE; Tue, 15 Oct 2013 04:55:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VVwf1-0003nu-Rw; Tue, 15 Oct 2013 04:55:11 +0000 Received: from co9ehsobe004.messaging.microsoft.com ([207.46.163.27] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VVwey-0003nH-FI for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2013 04:55:09 +0000 Received: from mail108-co9-R.bigfish.com (10.236.132.238) by CO9EHSOBE006.bigfish.com (10.236.130.69) with Microsoft SMTP Server id 14.1.225.22; Tue, 15 Oct 2013 04:54:44 +0000 Received: from mail108-co9 (localhost [127.0.0.1]) by mail108-co9-R.bigfish.com (Postfix) with ESMTP id 0882332004F; Tue, 15 Oct 2013 04:54:44 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275dhz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail108-co9 (localhost.localdomain [127.0.0.1]) by mail108-co9 (MessageSwitch) id 1381812882578275_32587; Tue, 15 Oct 2013 04:54:42 +0000 (UTC) Received: from CO9EHSMHS030.bigfish.com (unknown [10.236.132.244]) by mail108-co9.bigfish.com (Postfix) with ESMTP id 7DA88C0072; Tue, 15 Oct 2013 04:54:42 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS030.bigfish.com (10.236.130.40) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 15 Oct 2013 04:54:42 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 15 Oct 2013 04:54:41 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.131]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r9F4sbFk022294; Mon, 14 Oct 2013 21:54:38 -0700 From: Shawn Guo To: Subject: [PATCH 6/6] mmc: sdhci-esdhc-imx: create struct esdhc_soc_data Date: Tue, 15 Oct 2013 12:55:21 +0800 Message-ID: <1381812921-18525-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1381739024-24924-1-git-send-email-shawn.guo@linaro.org> References: <1381739024-24924-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131015_005508_753678_183DEF33 X-CRM114-Status: GOOD ( 15.81 ) X-Spam-Score: -3.5 (---) Cc: Chris Ball , Dong Aisheng , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, the SoC functional flags are passed through of_device_id.data by casting the integer to void pointer. This is less scalable considering we may have more SoC specific data to define in the future. Let's create a struct esdhc_soc_data to define SoC specific data like the 'flags' and pass the data using the structure pointer. Signed-off-by: Shawn Guo --- drivers/mmc/host/sdhci-esdhc-imx.c | 62 +++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index f2cd5b0..d3d34cf 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -100,19 +100,37 @@ */ #define ESDHC_FLAG_USDHC BIT(3) -#define IMX25_ESDHC (ESDHC_FLAG_NO_DMAS_BITS | ESDHC_FLAG_ENGCM07207) -#define IMX35_ESDHC (ESDHC_FLAG_ENGCM07207) -#define IMX51_ESDHC (0) -#define IMX53_ESDHC (ESDHC_FLAG_MULTIBLK_NO_INT) -#define IMX6Q_USDHC (ESDHC_FLAG_USDHC) +struct esdhc_soc_data { + u32 flags; +}; + +static struct esdhc_soc_data esdhc_imx25_data = { + .flags = ESDHC_FLAG_NO_DMAS_BITS | ESDHC_FLAG_ENGCM07207, +}; + +static struct esdhc_soc_data esdhc_imx35_data = { + .flags = ESDHC_FLAG_ENGCM07207, +}; + +static struct esdhc_soc_data esdhc_imx51_data = { + .flags = 0, +}; + +static struct esdhc_soc_data esdhc_imx53_data = { + .flags = ESDHC_FLAG_MULTIBLK_NO_INT, +}; + +static struct esdhc_soc_data esdhc_imx6q_data = { + .flags = ESDHC_FLAG_USDHC, +}; struct pltfm_imx_data { - int flags; u32 scratchpad; struct pinctrl *pinctrl; struct pinctrl_state *pins_default; struct pinctrl_state *pins_100mhz; struct pinctrl_state *pins_200mhz; + const struct esdhc_soc_data *socdata; struct esdhc_platform_data boarddata; struct clk *clk_ipg; struct clk *clk_ahb; @@ -128,13 +146,13 @@ struct pltfm_imx_data { static struct platform_device_id imx_esdhc_devtype[] = { { .name = "sdhci-esdhc-imx25", - .driver_data = IMX25_ESDHC, + .driver_data = (kernel_ulong_t) &esdhc_imx25_data, }, { .name = "sdhci-esdhc-imx35", - .driver_data = IMX35_ESDHC, + .driver_data = (kernel_ulong_t) &esdhc_imx35_data, }, { .name = "sdhci-esdhc-imx51", - .driver_data = IMX51_ESDHC, + .driver_data = (kernel_ulong_t) &esdhc_imx51_data, }, { /* sentinel */ } @@ -142,18 +160,18 @@ static struct platform_device_id imx_esdhc_devtype[] = { MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); static const struct of_device_id imx_esdhc_dt_ids[] = { - { .compatible = "fsl,imx25-esdhc", .data = (void *) IMX25_ESDHC, }, - { .compatible = "fsl,imx35-esdhc", .data = (void *) IMX35_ESDHC, }, - { .compatible = "fsl,imx51-esdhc", .data = (void *) IMX51_ESDHC, }, - { .compatible = "fsl,imx53-esdhc", .data = (void *) IMX53_ESDHC, }, - { .compatible = "fsl,imx6q-usdhc", .data = (void *) IMX6Q_USDHC, }, + { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, + { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, + { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, + { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, + { .compatible = "fsl,imx6q-usdhc", .data = &esdhc_imx6q_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) { - return !!(data->flags & ESDHC_FLAG_USDHC); + return !!(data->socdata->flags & ESDHC_FLAG_USDHC); } static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) @@ -251,7 +269,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) } } - if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) + if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) && (reg == SDHCI_INT_STATUS) && (val & SDHCI_INT_DATA_END))) { u32 v; @@ -350,7 +368,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); return; case SDHCI_TRANSFER_MODE: - if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) + if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) && (host->cmd->opcode == SD_IO_RW_EXTENDED) && (host->cmd->data->blocks > 1) && (host->cmd->data->flags & MMC_DATA_READ)) { @@ -382,7 +400,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) val |= SDHCI_CMD_ABORTCMD; if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && - (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) + (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) imx_data->multiblock_status = MULTIBLK_IN_PROCESS; if (esdhc_is_usdhc(imx_data)) @@ -419,7 +437,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) /* ensure the endianness */ new_val |= ESDHC_HOST_CONTROL_LE; /* bits 8&9 are reserved on mx25 */ - if (!(imx_data->flags & ESDHC_FLAG_NO_DMAS_BITS)) { + if (!(imx_data->socdata->flags & ESDHC_FLAG_NO_DMAS_BITS)) { /* DMA mode bits are shifted */ new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; } @@ -838,8 +856,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) goto free_sdhci; } - imx_data->flags = of_id ? (int) of_id->data : - pdev->id_entry->driver_data; + imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) + pdev->id_entry->driver_data; pltfm_host->priv = imx_data; imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); @@ -882,7 +900,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; - if (imx_data->flags & ESDHC_FLAG_ENGCM07207) + if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK | SDHCI_QUIRK_BROKEN_ADMA;