From patchwork Tue Oct 15 15:14:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 3046101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 075EE9F2B6 for ; Tue, 15 Oct 2013 15:19:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 463A3202B8 for ; Tue, 15 Oct 2013 15:18:55 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E29B0201FF for ; Tue, 15 Oct 2013 15:18:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW6NI-0003Pq-Nd; Tue, 15 Oct 2013 15:17:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW6Mu-0003X7-GX; Tue, 15 Oct 2013 15:17:08 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VW6Mp-0003UF-1y for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2013 15:17:04 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 15 Oct 2013 08:16:41 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 15 Oct 2013 08:12:18 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 15 Oct 2013 08:12:18 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.327.1; Tue, 15 Oct 2013 08:16:41 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 15 Oct 2013 08:16:41 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r9FFG4GK024948; Tue, 15 Oct 2013 08:16:38 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver Subject: [PATCH v2 3/7] clk: tegra124: Add common clk IDs to clk-id.h Date: Tue, 15 Oct 2013 18:14:46 +0300 Message-ID: <1381850098-12357-4-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1381850098-12357-1-git-send-email-pdeschrijver@nvidia.com> References: <1381850098-12357-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131015_111703_292555_AB4BE957 X-CRM114-Status: UNSURE ( 9.39 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.6 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Prashant Gaikwad , Mike Turquette , Pawel Moll , Stephen Warren , Ian Campbell , linux-kernel@vger.kernel.org, Rob Herring , Thierry Reding , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 22e2e8e..836b054 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -7,8 +7,10 @@ enum clk_id { tegra_clk_actmon, tegra_clk_adx, + tegra_clk_adx1, tegra_clk_afi, tegra_clk_amx, + tegra_clk_amx1, tegra_clk_apbdma, tegra_clk_apbif, tegra_clk_audio0, @@ -35,6 +37,7 @@ enum clk_id { tegra_clk_cilcd, tegra_clk_cile, tegra_clk_clk_32k, + tegra_clk_clk72Mhz, tegra_clk_clk_m, tegra_clk_clk_m_div2, tegra_clk_clk_m_div4, @@ -44,6 +47,8 @@ enum clk_id { tegra_clk_clk_out_2_mux, tegra_clk_clk_out_3, tegra_clk_clk_out_3_mux, + tegra_clk_cml0, + tegra_clk_cml1, tegra_clk_csi, tegra_clk_csite, tegra_clk_csus, @@ -58,6 +63,7 @@ enum clk_id { tegra_clk_disp1, tegra_clk_disp2, tegra_clk_dp2, + tegra_clk_dpaux, tegra_clk_dsia, tegra_clk_dsialp, tegra_clk_dsia_mux, @@ -66,6 +72,7 @@ enum clk_id { tegra_clk_dsib_mux, tegra_clk_dtv, tegra_clk_emc, + tegra_clk_entropy, tegra_clk_epp, tegra_clk_epp_8, tegra_clk_extern1, @@ -73,6 +80,7 @@ enum clk_id { tegra_clk_extern3, tegra_clk_fuse, tegra_clk_fuse_burn, + tegra_clk_gpu, tegra_clk_gr2d, tegra_clk_gr2d_8, tegra_clk_gr3d, @@ -82,6 +90,7 @@ enum clk_id { tegra_clk_hda2codec_2x, tegra_clk_hda2hdmi, tegra_clk_hdmi, + tegra_clk_hdmi_audio, tegra_clk_host1x, tegra_clk_host1x_8, tegra_clk_i2c1, @@ -89,6 +98,7 @@ enum clk_id { tegra_clk_i2c3, tegra_clk_i2c4, tegra_clk_i2c5, + tegra_clk_i2c6, tegra_clk_i2cslow, tegra_clk_i2s0, tegra_clk_i2s0_sync, @@ -101,6 +111,8 @@ enum clk_id { tegra_clk_i2s4, tegra_clk_i2s4_sync, tegra_clk_isp, + tegra_clk_isp_8, + tegra_clk_ispb, tegra_clk_kbc, tegra_clk_kfuse, tegra_clk_la, @@ -115,17 +127,20 @@ enum clk_id { tegra_clk_ndspeed_8, tegra_clk_nor, tegra_clk_owr, + tegra_clk_pcie, tegra_clk_pclk, tegra_clk_pll_a, tegra_clk_pll_a_out0, tegra_clk_pll_c, tegra_clk_pll_c2, tegra_clk_pll_c3, + tegra_clk_pll_c4, tegra_clk_pll_c_out1, tegra_clk_pll_d, tegra_clk_pll_d2, tegra_clk_pll_d2_out0, tegra_clk_pll_d_out0, + tegra_clk_pll_dp, tegra_clk_pll_e_out0, tegra_clk_pll_m, tegra_clk_pll_m_out1, @@ -135,6 +150,7 @@ enum clk_id { tegra_clk_pll_p_out2_int, tegra_clk_pll_p_out3, tegra_clk_pll_p_out4, + tegra_clk_pll_p_out5, tegra_clk_pll_ref, tegra_clk_pll_re_out, tegra_clk_pll_re_vco, @@ -169,6 +185,7 @@ enum clk_id { tegra_clk_sdmmc4, tegra_clk_se, tegra_clk_soc_therm, + tegra_clk_sor0, tegra_clk_spdif, tegra_clk_spdif_2x, tegra_clk_spdif_in, @@ -195,8 +212,11 @@ enum clk_id { tegra_clk_vfir, tegra_clk_vi, tegra_clk_vi_8, + tegra_clk_vic03, + tegra_clk_vim2_clk, tegra_clk_vimclk_sync, tegra_clk_vi_sensor, + tegra_clk_vi_sensor2, tegra_clk_vi_sensor_8, tegra_clk_xusb_dev, tegra_clk_xusb_dev_src,