| Message ID | 1383736008-22764-1-git-send-email-tomi.valkeinen@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Nov 06, 2013 at 01:06:48PM +0200, Tomi Valkeinen wrote: > This means that the following code works a bit oddly: > > rate = clk_round_rate(clk, 123428572); > clk_set_rate(clk, rate); You're right, but the above sequence is quite a crass thing to do. Why? clk_round_rate() returns the clock rate that clk_set_rate() would give you if you were to use this sequence: clk_rate_rate(clk, 123428572); rate = clk_get_rate(clk); The difference is that it doesn't change the actual clock rate itself; clk_round_rate() is meant to answer the question: "If I were to set _this_ rate, what clock rate would the clock give me?" thereby providing a method for drivers to inquire what the effect would be when changing such a clock without actually affecting it. So please, don't use clk_round_rate() followed by clk_set_rate().
On 2013-11-06 13:15, Russell King - ARM Linux wrote: > On Wed, Nov 06, 2013 at 01:06:48PM +0200, Tomi Valkeinen wrote: >> This means that the following code works a bit oddly: >> >> rate = clk_round_rate(clk, 123428572); >> clk_set_rate(clk, rate); > > You're right, but the above sequence is quite a crass thing to do. Why? Do you mean that you think the fix is right, but the above example sequence is silly, or that the fix is not needed either? > clk_round_rate() returns the clock rate that clk_set_rate() would give > you if you were to use this sequence: > > clk_rate_rate(clk, 123428572); > rate = clk_get_rate(clk); > > The difference is that it doesn't change the actual clock rate itself; > clk_round_rate() is meant to answer the question: > > "If I were to set _this_ rate, what clock rate would > the clock give me?" > > thereby providing a method for drivers to inquire what the effect would > be when changing such a clock without actually affecting it. > > So please, don't use clk_round_rate() followed by clk_set_rate(). Ok, if defined like that, then the current behavior is logical. The comment in clk.h says "adjust a rate to the exact rate a clock can provide", which does not contradict with what you said, but doesn't really confirm it either. If I get "the exact rate a clock can provide" I don't see why I can't use that exact clock rate for clk_set_rate. Maybe the comment should be improved to state explicitly what it does. However, how about the following sequence: clk_set_rate(clk, 123428572); rate = clk_get_rate(clk); clk_set_rate(clk, rate); I didn't test that but it should result in the clock first set to 123428571, and then to 108000000. Obviously pointless if done exactly like that, but I don't see why the above code sequence is wrong, yet it gives a bit surprising result. Tomi
Mike, ping. Tomi On 06/11/13 13:06, Tomi Valkeinen wrote: > clk-divider.c does not calculate the rates consistently at the moment. > > As an example, on OMAP3 we have a clock divider with a source clock of > 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: > > 6: 144000000 > 7: 123428571.428571... > 8: 108000000 > > Calling clk_round_rate() with the rate in the first column will give the > rate in the second column: > > 144000000 -> 144000000 > 143999999 -> 123428571 > 123428572 -> 123428571 > 123428571 -> 108000000 > > Note how clk_round_rate() returns 123428571 for rates from 123428572 to > 143999999, which is mathematically correct, but when clk_round_rate() is > called with 123428571, the returned value is surprisingly 108000000. > > This means that the following code works a bit oddly: > > rate = clk_round_rate(clk, 123428572); > clk_set_rate(clk, rate); > > As clk_set_rate() also does clock rate rounding, the result is that the > clock is set to the rate of 108000000, not 123428571 returned by the > clk_round_rate. > > This patch changes the clk-divider.c to use DIV_ROUND_UP when > calculating the rate. This gives the following behavior which fixes the > inconsistency: > > 144000000 -> 144000000 > 143999999 -> 123428572 > 123428572 -> 123428572 > 123428571 -> 108000000 > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > Cc: Mike Turquette <mturquette@linaro.org> > --- > drivers/clk/clk-divider.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index 8d3009e..43348f3 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c > @@ -24,7 +24,7 @@ > * Traits of this clock: > * prepare - clk_prepare only ensures that parents are prepared > * enable - clk_enable only ensures that parents are enabled > - * rate - rate is adjustable. clk->rate = parent->rate / divisor > + * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor) > * parent - fixed parent. No clk_set_parent support > */ > > @@ -115,7 +115,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, > return parent_rate; > } > > - return parent_rate / div; > + return DIV_ROUND_UP(parent_rate, div); > } > > /* > @@ -185,7 +185,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, > } > parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), > MULT_ROUND_UP(rate, i)); > - now = parent_rate / i; > + now = DIV_ROUND_UP(parent_rate, i); > if (now <= rate && now > best) { > bestdiv = i; > best = now; > @@ -207,7 +207,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, > int div; > div = clk_divider_bestdiv(hw, rate, prate); > > - return *prate / div; > + return DIV_ROUND_UP(*prate, div); > } > > static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, > @@ -218,7 +218,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, > unsigned long flags = 0; > u32 val; > > - div = parent_rate / rate; > + div = DIV_ROUND_UP(parent_rate, rate); > value = _get_val(divider, div); > > if (value > div_mask(divider)) >
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 8d3009e..43348f3 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -24,7 +24,7 @@ * Traits of this clock: * prepare - clk_prepare only ensures that parents are prepared * enable - clk_enable only ensures that parents are enabled - * rate - rate is adjustable. clk->rate = parent->rate / divisor + * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor) * parent - fixed parent. No clk_set_parent support */ @@ -115,7 +115,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, return parent_rate; } - return parent_rate / div; + return DIV_ROUND_UP(parent_rate, div); } /* @@ -185,7 +185,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, } parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), MULT_ROUND_UP(rate, i)); - now = parent_rate / i; + now = DIV_ROUND_UP(parent_rate, i); if (now <= rate && now > best) { bestdiv = i; best = now; @@ -207,7 +207,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, int div; div = clk_divider_bestdiv(hw, rate, prate); - return *prate / div; + return DIV_ROUND_UP(*prate, div); } static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, @@ -218,7 +218,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long flags = 0; u32 val; - div = parent_rate / rate; + div = DIV_ROUND_UP(parent_rate, rate); value = _get_val(divider, div); if (value > div_mask(divider))
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Mike Turquette <mturquette@linaro.org> --- drivers/clk/clk-divider.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)