From patchwork Thu Nov 7 08:45:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 3151741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BBD1FBEEB2 for ; Thu, 7 Nov 2013 08:59:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AEB6E20630 for ; Thu, 7 Nov 2013 08:59:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 81CFD202C3 for ; Thu, 7 Nov 2013 08:59:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VeLEV-0005J1-LR; Thu, 07 Nov 2013 08:46:31 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VeLEK-0001Ad-IB; Thu, 07 Nov 2013 08:46:20 +0000 Received: from smtp39.i.mail.ru ([94.100.177.99]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VeLDm-00016n-Su for linux-arm-kernel@lists.infradead.org; Thu, 07 Nov 2013 08:45:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=hZ6puUXz2dnAq1CCY5WwNOc/fF/DyxFr2XCBgUflwPE=; b=pHaj2G24pKcHhnf81HWjFVhl33T7K8Gy5KmQahkyS1fdRCXF2QCU/2jydLhZeCSAInqKqFF3CLLjRhjVgyWp2fIPdkGAMvvs6jU0sVcRvZPRu31JjNKwNxwUwolKGwgaxD0omOlIGDqTUFGBe+7+2Gorm9T8qOOV8sLKYPbShkk=; Received: from [217.119.30.118] (port=18042 helo=shc.milas.spb.ru) by smtp39.i.mail.ru with esmtpa (envelope-from ) id 1VeLDS-0002H6-Jp; Thu, 07 Nov 2013 12:45:27 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/5] ARM: dts: i.MX51: Add missing pinctrl definitions Date: Thu, 7 Nov 2013 12:45:07 +0400 Message-Id: <1383813908-26571-4-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1383813908-26571-1-git-send-email-shc_work@mail.ru> References: <1383813908-26571-1-git-send-email-shc_work@mail.ru> X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131107_034547_474900_02C29AF9 X-CRM114-Status: UNSURE ( 7.34 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.2 (-) Cc: Shawn Guo , Russell King , Alexander Shiyan , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM,RCVD_IN_DNSWL_MED,RCVD_IN_SORBS_WEB,RP_MATCHES_RCVD, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds missing pinctrl definitions for Keypad (columns 4 and 5), NFC, 1-Wire and WEIM. Signed-off-by: Alexander Shiyan --- arch/arm/boot/dts/imx51-pingrp.h | 93 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm/boot/dts/imx51-pingrp.h b/arch/arm/boot/dts/imx51-pingrp.h index 550d0d1..41a67ba 100644 --- a/arch/arm/boot/dts/imx51-pingrp.h +++ b/arch/arm/boot/dts/imx51-pingrp.h @@ -157,6 +157,32 @@ MX51_PAD_KEY_COL2__KEY_COL2 0xe8 \ MX51_PAD_KEY_COL3__KEY_COL3 0xe8 +#define MX51_KPP_COL45_PINGRP1 \ + MX51_PAD_KEY_COL4__KEY_COL4 0xe8 \ + MX51_PAD_KEY_COL5__KEY_COL5 0xe8 + +#define MX51_NFC_PINGRP1 \ + MX51_PAD_NANDF_D0__NANDF_D0 0x80000000 \ + MX51_PAD_NANDF_D1__NANDF_D1 0x80000000 \ + MX51_PAD_NANDF_D2__NANDF_D2 0x80000000 \ + MX51_PAD_NANDF_D3__NANDF_D3 0x80000000 \ + MX51_PAD_NANDF_D4__NANDF_D4 0x80000000 \ + MX51_PAD_NANDF_D5__NANDF_D5 0x80000000 \ + MX51_PAD_NANDF_D6__NANDF_D6 0x80000000 \ + MX51_PAD_NANDF_D7__NANDF_D7 0x80000000 \ + MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000 \ + MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000 \ + MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000 \ + MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000 \ + MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000 + +#define MX51_NFC_CS0_PINGRP1 \ + MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000 \ + MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000 + +#define MX51_OWIRE_PINGRP1 \ + X51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 + #define MX51_PATA_PINGRP1 \ MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 \ MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 \ @@ -244,4 +270,71 @@ MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 \ MX51_PAD_EIM_A26__USBH2_STP 0x1e5 +#define MX51_WEIM_PINGRP1 \ + MX51_PAD_EIM_DA0__EIM_DA0 0x80000000 \ + MX51_PAD_EIM_DA1__EIM_DA1 0x80000000 \ + MX51_PAD_EIM_DA2__EIM_DA2 0x80000000 \ + MX51_PAD_EIM_DA3__EIM_DA3 0x80000000 \ + MX51_PAD_EIM_DA4__EIM_DA4 0x80000000 \ + MX51_PAD_EIM_DA5__EIM_DA5 0x80000000 \ + MX51_PAD_EIM_DA6__EIM_DA6 0x80000000 \ + MX51_PAD_EIM_DA7__EIM_DA7 0x80000000 \ + MX51_PAD_EIM_DA8__EIM_DA8 0x80000000 \ + MX51_PAD_EIM_DA9__EIM_DA9 0x80000000 \ + MX51_PAD_EIM_DA10__EIM_DA10 0x80000000 \ + MX51_PAD_EIM_DA11__EIM_DA11 0x80000000 \ + MX51_PAD_EIM_DA12__EIM_DA12 0x80000000 \ + MX51_PAD_EIM_DA13__EIM_DA13 0x80000000 \ + MX51_PAD_EIM_DA14__EIM_DA14 0x80000000 \ + MX51_PAD_EIM_DA15__EIM_DA15 0x80000000 \ + MX51_PAD_EIM_A16__EIM_A16 0x80000000 \ + MX51_PAD_EIM_A17__EIM_A17 0x80000000 \ + MX51_PAD_EIM_A18__EIM_A18 0x80000000 \ + MX51_PAD_EIM_A19__EIM_A19 0x80000000 \ + MX51_PAD_EIM_A20__EIM_A20 0x80000000 \ + MX51_PAD_EIM_A21__EIM_A21 0x80000000 \ + MX51_PAD_EIM_A22__EIM_A22 0x80000000 \ + MX51_PAD_EIM_A23__EIM_A23 0x80000000 \ + MX51_PAD_EIM_A24__EIM_A24 0x80000000 \ + MX51_PAD_EIM_A25__EIM_A25 0x80000000 \ + MX51_PAD_EIM_A26__EIM_A26 0x80000000 \ + MX51_PAD_EIM_A27__EIM_A27 0x80000000 \ + MX51_PAD_EIM_D16__EIM_D16 0x80000000 \ + MX51_PAD_EIM_D17__EIM_D17 0x80000000 \ + MX51_PAD_EIM_D18__EIM_D18 0x80000000 \ + MX51_PAD_EIM_D19__EIM_D19 0x80000000 \ + MX51_PAD_EIM_D20__EIM_D20 0x80000000 \ + MX51_PAD_EIM_D21__EIM_D21 0x80000000 \ + MX51_PAD_EIM_D22__EIM_D22 0x80000000 \ + MX51_PAD_EIM_D23__EIM_D23 0x80000000 \ + MX51_PAD_EIM_D24__EIM_D24 0x80000000 \ + MX51_PAD_EIM_D25__EIM_D25 0x80000000 \ + MX51_PAD_EIM_D26__EIM_D26 0x80000000 \ + MX51_PAD_EIM_D27__EIM_D27 0x80000000 \ + MX51_PAD_EIM_D28__EIM_D28 0x80000000 \ + MX51_PAD_EIM_D29__EIM_D29 0x80000000 \ + MX51_PAD_EIM_D30__EIM_D30 0x80000000 \ + MX51_PAD_EIM_D31__EIM_D31 0x80000000 \ + MX51_PAD_EIM_OE__EIM_OE 0x80000000 \ + MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000 \ + MX51_PAD_EIM_LBA__EIM_LBA 0x80000000 + +#define MX51_WEIM_CS0_PINGRP1 \ + MX51_PAD_EIM_CS0__EIM_CS0 0x80000000 + +#define MX51_WEIM_CS1_PINGRP1 \ + MX51_PAD_EIM_CS1__EIM_CS1 0x80000000 + +#define MX51_WEIM_CS2_PINGRP1 \ + MX51_PAD_EIM_CS2__EIM_CS2 0x80000000 + +#define MX51_WEIM_CS3_PINGRP1 \ + MX51_PAD_EIM_CS3__EIM_CS3 0x80000000 + +#define MX51_WEIM_CS4_PINGRP1 \ + MX51_PAD_EIM_CS4__EIM_CS4 0x80000000 + +#define MX51_WEIM_CS5_PINGRP1 \ + MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 + #endif /* __DTS_IMX51_PINGRP_H */