From patchwork Fri Nov 8 05:38:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 3156291 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E88FB9F440 for ; Fri, 8 Nov 2013 05:40:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B4EC520497 for ; Fri, 8 Nov 2013 05:40:55 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4623E20490 for ; Fri, 8 Nov 2013 05:40:54 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Veenf-00014w-KW; Fri, 08 Nov 2013 05:40:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VeenT-0003Iq-Qi; Fri, 08 Nov 2013 05:39:55 +0000 Received: from mail-pb0-f50.google.com ([209.85.160.50]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VeenK-0003Gr-PU for linux-arm-kernel@lists.infradead.org; Fri, 08 Nov 2013 05:39:49 +0000 Received: by mail-pb0-f50.google.com with SMTP id uo15so1656353pbc.37 for ; Thu, 07 Nov 2013 21:39:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LzpTyMsAMTn5R7dvOei2qqx6ascCSgwz+y5vV4L7SYs=; b=bfDPls1SVeHHmTHUfrZQ7DnDVqGQNj9EPvm/QSelRRZ/gRK46c34uHC2JvIbY3R1hJ 2DRQPETIMCJIVp45oBEL0XdA+xI9h/HQR9ndArYSvqFl3079iDe1MWL+z9kMIfw94QXC 80p/9AS/iDwMG8R5a1SH6fwKo5VOA2h2qsjwVIdpubKLA+8qCEomqsghgQ1gTovLZCiN vA/5QF04XJ/ph0a0nT141KDhHOGIwX0nCm7jh7z5sPmgCcQzL2/7otcCr8lzQ5RWbK55 RCYOyy6j8slMZtGFhc0RpNXtxd8hKlSmeM3Gmj284m1MvOB5eW3C+4HVTLDpZtfQvpGG sR1w== X-Gm-Message-State: ALoCoQlHBxF7W2humRiq1pv04Jr0wED3VBIDCsNkPunYQWTsYQVzMr2xz9I1EzQyE1yYup/T4H1O X-Received: by 10.66.216.162 with SMTP id or2mr13652370pac.179.1383889165105; Thu, 07 Nov 2013 21:39:25 -0800 (PST) Received: from localhost.localdomain ([223.240.21.30]) by mx.google.com with ESMTPSA id rv9sm9285880pbc.4.2013.11.07.21.39.18 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Nov 2013 21:39:24 -0800 (PST) From: Zhangfei Gao To: Chris Ball , Jaehoon Chung , Seungwon Jeon , Kumar Gala Subject: [PATCH 2/2] mmc: dw_mmc: add dw_mmc-k3 for k3 platform Date: Fri, 8 Nov 2013 13:38:47 +0800 Message-Id: <1383889128-12540-3-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383889128-12540-1-git-send-email-zhangfei.gao@linaro.org> References: <1383889128-12540-1-git-send-email-zhangfei.gao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131108_003947_057639_F55D1A0A X-CRM114-Status: GOOD ( 23.29 ) X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zhangfei Gao X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add dw_mmc-k3.c for k3v2, support sd/emmc Signed-off-by: Zhangfei Gao Tested-by: Zhigang Wang --- .../devicetree/bindings/mmc/k3-dw-mshc.txt | 83 +++++++ drivers/mmc/host/Kconfig | 10 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/dw_mmc-k3.c | 247 ++++++++++++++++++++ 4 files changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt create mode 100644 drivers/mmc/host/dw_mmc-k3.c diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt new file mode 100644 index 0000000..ea858f4 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt @@ -0,0 +1,83 @@ +* Hisilicon specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +Read synopsis-dw-mshc.txt for more details +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsis-dw-mshc.txt and the properties used by the Hisilicon specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be + - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 + specific extentions. +* reg: should be address and size of mmc controller +* vmmc-supply: should be vmmc used in dwmmc +* fifo-depth: should be provided if register can not provide correct value +* tuning-table: should be array to tune mmc controller, including clock rate + to be set and values for setting optional register. + +Optional properties: + +/* These registers from pctrl node used for tuning mmc controller if required */ +* clken-reg: should be clock enable register and offset bit +* drv-sel-reg: should be driver delay select register, start bit and bits numbers +* sam-sel-reg: should be sample delay select register, start bit and bits numbers +* div-reg: should be divider register, start bit and bits numbers + +Example: + + /* SoC portion */ + dwmmc_0: dwmmc0@fcd03000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd03000 0x1000>; + interrupts = <0 16 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_sd>, <&clk_ddrc_per>; + clock-names = "ciu", "biu"; + clken-reg = <0x1f8 0>; + drv-sel-reg = <0x1f8 4 4>; + sam-sel-reg = <0x1f8 8 4>; + div-reg = <0x1f8 1 3>; + tuning-table = + <180000000 6 6 13 13 25000000>, + <0 0 0 0 0 0>, + <360000000 6 4 2 0 50000000>, + <180000000 6 4 13 13 25000000>, + <360000000 6 4 2 0 50000000>, + <720000000 6 1 9 4 100000000>, + <0 0 0 0 0 0>, + <360000000 7 1 3 0 50000000>; + }; + + /* Board portion */ + dwmmc0@fcd03000 { + num-slots = <1>; + vmmc-supply = <&ldo12>; + fifo-depth = <0x100>; + supports-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>; + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + cd-gpios = <&gpio10 3 0>; + }; + }; + +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 7fc5099..45aaa2d 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -575,6 +575,16 @@ config MMC_DW_SOCFPGA This selects support for Altera SoCFPGA specific extensions to the Synopsys DesignWare Memory Card Interface driver. +config MMC_DW_K3 + tristate "K3 specific extensions for Synopsys DW Memory Card Interface" + depends on MMC_DW + select MMC_DW_PLTFM + select MMC_DW_IDMAC + help + This selects support for Hisilicon K3 SoC specific extensions to the + Synopsys DesignWare Memory Card Interface driver. Select this option + for platforms based on Hisilicon K3 SoC's. + config MMC_DW_PCI tristate "Synopsys Designware MCI support on PCI bus" depends on MMC_DW && PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index c41d0c3..64f5f8d 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_MMC_DW) += dw_mmc.o obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o obj-$(CONFIG_MMC_DW_SOCFPGA) += dw_mmc-socfpga.o +obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c new file mode 100644 index 0000000..881d2f4 --- /dev/null +++ b/drivers/mmc/host/dw_mmc-k3.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#include "dw_mmc.h" +#include "dw_mmc-pltfm.h" + +#define TABLE_WIDTH 6 +#define TABLE_HEIGHT 8 +struct dw_mci_k3_priv_data { + int old_timing; + u32 table[TABLE_WIDTH * TABLE_HEIGHT]; + u32 clken_reg; + u32 clken_bit; + u32 sam_reg; + u32 sam_off; + u32 sam_bits; + u32 drv_reg; + u32 drv_off; + u32 drv_bits; + u32 div_reg; + u32 div_off; + u32 div_bits; +}; + +static void __iomem *pctrl; +static DEFINE_SPINLOCK(mmc_tuning_lock); + +static u32 dw_mci_k3_delay(u32 val, u32 para, u32 off, u32 len) +{ + u32 i; + + if (para >= 0) { + for (i = 0; i < len; i++) { + if (para % 2) + val |= 1 << (off + i); + else + val &= ~(1 << (off + i)); + para = para >> 1; + } + } + return val; +} + +static void dw_mci_k3_set_timing(struct dw_mci_k3_priv_data *priv, + u32 sam, u32 drv, u32 div) +{ + u32 val; + unsigned long flags; + + if (!pctrl || !priv->clken_reg || !priv->sam_reg + || !priv->drv_reg || !priv->div_reg) + return; + + spin_lock_irqsave(&mmc_tuning_lock, flags); + + val = readl(pctrl + priv->clken_reg); + val &= ~(1 << priv->clken_bit); + writel(val, pctrl + priv->clken_reg); + + val = readl(pctrl + priv->sam_reg); + val = dw_mci_k3_delay(val, sam, priv->sam_off, priv->sam_bits); + writel(val, pctrl + priv->sam_reg); + + val = readl(pctrl + priv->drv_reg); + val = dw_mci_k3_delay(val, drv, priv->drv_off, priv->drv_bits); + writel(val, pctrl + priv->drv_reg); + + val = readl(pctrl + priv->div_reg); + val = dw_mci_k3_delay(val, div, priv->div_off, priv->div_bits); + writel(val, pctrl + priv->div_reg); + + val = readl(pctrl + priv->clken_reg); + val |= 1 << priv->clken_bit; + writel(val, pctrl + priv->clken_reg); + + spin_unlock_irqrestore(&mmc_tuning_lock, flags); +} + +static void dw_mci_k3_tun(struct dw_mci *host, int timing) +{ + struct dw_mci_k3_priv_data *priv = host->priv; + u32 *table = &priv->table[TABLE_WIDTH * timing]; + int ret; + + if (priv->old_timing == timing) + return; + + ret = clk_set_rate(host->ciu_clk, table[0]); + if (ret) { + dev_err(host->dev, "clk_set_rate failed\n"); + return; + } + dw_mci_k3_set_timing(priv, (table[3] + table[4]) / 2, + table[2], table[1]); + host->bus_hz = table[5]; + priv->old_timing = timing; +} + +static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios) +{ + dw_mci_k3_tun(host, ios->timing); +} + +static int dw_mci_k3_setup_clock(struct dw_mci *host) +{ + dw_mci_k3_tun(host, MMC_TIMING_LEGACY); + return 0; +} + +static int dw_mci_k3_parse_dt(struct dw_mci *host) +{ + struct dw_mci_k3_priv_data *priv; + struct device_node *np = host->dev->of_node, *node; + u32 data[3]; + int ret; + + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(host->dev, "mem alloc failed for private data\n"); + return -ENOMEM; + } + priv->old_timing = -1; + host->priv = priv; + + ret = of_property_read_u32_array(host->dev->of_node, "tuning-table", + priv->table, TABLE_WIDTH * TABLE_HEIGHT); + if (ret) { + dev_err(host->dev, "not found tuning-table\n"); + return -EINVAL; + } + + if (!pctrl) { + node = of_find_compatible_node(NULL, NULL, "hisilicon,pctrl"); + pctrl = of_iomap(node, 0); + } + + ret = of_property_read_u32_array(np, "clken-reg", data, 2); + if (!ret) { + priv->clken_reg = data[0]; + priv->clken_bit = data[1]; + } + + ret = of_property_read_u32_array(np, "drv-sel-reg", data, 3); + if (!ret) { + priv->drv_reg = data[0]; + priv->drv_off = data[1]; + priv->drv_bits = data[2]; + } + + ret = of_property_read_u32_array(np, "sam-sel-reg", data, 3); + if (!ret) { + priv->sam_reg = data[0]; + priv->sam_off = data[1]; + priv->sam_bits = data[2]; + } + + ret = of_property_read_u32_array(np, "div-reg", data, 3); + if (!ret) { + priv->div_reg = data[0]; + priv->div_off = data[1]; + priv->div_bits = data[2]; + } + + return 0; +} + +static unsigned long k3_dwmmc_caps[4] = { + MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED, + MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, + 0, + 0, +}; + +static const struct dw_mci_drv_data k3_drv_data = { + .caps = k3_dwmmc_caps, + .set_ios = dw_mci_k3_set_ios, + .setup_clock = dw_mci_k3_setup_clock, + .parse_dt = dw_mci_k3_parse_dt, +}; + +static const struct of_device_id dw_mci_k3_match[] = { + { .compatible = "hisilicon,hi4511-dw-mshc", + .data = &k3_drv_data, }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_mci_k3_match); + +static int dw_mci_k3_probe(struct platform_device *pdev) +{ + const struct dw_mci_drv_data *drv_data; + const struct of_device_id *match; + + match = of_match_node(dw_mci_k3_match, pdev->dev.of_node); + drv_data = match->data; + + return dw_mci_pltfm_register(pdev, drv_data); +} + +static int dw_mci_k3_suspend(struct device *dev) +{ + struct dw_mci *host = dev_get_drvdata(dev); + + return dw_mci_suspend(host); +} + +static int dw_mci_k3_resume(struct device *dev) +{ + struct dw_mci *host = dev_get_drvdata(dev); + struct dw_mci_k3_priv_data *priv = host->priv; + + priv->old_timing = -1; + dw_mci_k3_tun(host, MMC_TIMING_LEGACY); + + return dw_mci_resume(host); +} + +SIMPLE_DEV_PM_OPS(dw_mci_k3_pmops, dw_mci_k3_suspend, dw_mci_k3_resume); + +static struct platform_driver dw_mci_k3_pltfm_driver = { + .probe = dw_mci_k3_probe, + .remove = dw_mci_pltfm_remove, + .driver = { + .name = "dwmmc_k3", + .of_match_table = dw_mci_k3_match, + .pm = &dw_mci_k3_pmops, + }, +}; + +module_platform_driver(dw_mci_k3_pltfm_driver); + +MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:dwmmc-k3");