From patchwork Sun Nov 10 09:23:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Lei X-Patchwork-Id: 3165021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CA8BEC045B for ; Sun, 10 Nov 2013 10:16:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E1A0C20265 for ; Sun, 10 Nov 2013 10:16:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 838B620263 for ; Sun, 10 Nov 2013 10:16:32 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VfS4C-0002tz-Qh; Sun, 10 Nov 2013 10:16:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VfS4A-00011Q-Ht; Sun, 10 Nov 2013 10:16:26 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VfS46-000107-4X for linux-arm-kernel@lists.infradead.org; Sun, 10 Nov 2013 10:16:23 +0000 Received: by mail-pa0-f51.google.com with SMTP id ld10so4068989pab.24 for ; Sun, 10 Nov 2013 02:15:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id; bh=2d9SLIzrDJKI12arsRck041Sq5uFsMeP3u/9WD4jx9Y=; b=T4SCou8NipUEELg3N1sZw0MopJHEYSDjqKbanIdS8UoX7EaYfQDN+RT5FEurENxM4f h/QZK/+fWI3E30z2zRHM1kphnmYZWUcbxO6r4BCXTbyZ2M4SeMTCrXa0E22OnaeziAl9 U5zxp5q0jCjeL9f0CMtpGDoA8koDFWmGfmfeN4V4vs5Z1+d/tOE9YAex1QeZdI7ekhAO C15dzgMqqpapqTOEk02QtMVUEL/N7Wq6sQBMG/FQ2+caL/cpaDYVkM06Zxpj/ag4S95U dGqoR1SCjFtWGDdkaD7bDIwZ/08zrlmZYgOZAh1uB+cNHzDhkv2erzE3eksd11Qwwg0B pikA== X-Received: by 10.68.4.232 with SMTP id n8mr24592396pbn.9.1384075442334; Sun, 10 Nov 2013 01:24:02 -0800 (PST) Received: from localhost ([14.155.220.48]) by mx.google.com with ESMTPSA id qz9sm23378242pbc.3.2013.11.10.01.23.53 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 10 Nov 2013 01:24:01 -0800 (PST) From: Ming Lei To: Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: emulate aarch32 CP15 barriers if needed Date: Sun, 10 Nov 2013 17:23:23 +0800 Message-Id: <1384075404-19605-1-git-send-email-ming.lei@canonical.com> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131110_051622_256638_CC9A6F15 X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -2.6 (--) Cc: Ming Lei , Will Deacon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CP15BEN of SCTLR_EL1 may not be implemented, so we need to emulate these three CP15 barriers to avoid breaking aarch32 applications since they can be used in user mode. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Ming Lei --- arch/arm64/kernel/traps.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 7ffaddd..c9f009d 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -257,6 +257,34 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, die(str, regs, err); } +/* + * CP15BEN of SCTLR_EL1 may not be implemented, so emulate + * these three instructions when they trap in + */ +static int aarch32_cp15_barriers(struct pt_regs *regs) +{ + unsigned int instr; + void __user *pc = (void __user *)instruction_pointer(regs); + + if (!compat_user_mode(regs)) + return -EFAULT; + + get_user(instr, (u32 __user *)pc); + instr &= ~0xf000f000; + + if (instr == 0x0e070fba) /* CP15DMB */ + smp_mb(); + else if (instr == 0x0e070f9a) /* CP15DSB */ + dsb(); + else if (instr == 0x0e070f95) /* CP15ISB */ + isb(); + else + return -EFAULT; + + regs->pc += 4; + return 0; +} + asmlinkage void __exception do_undefinstr(struct pt_regs *regs) { siginfo_t info; @@ -266,6 +294,10 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) if (!aarch32_break_handler(regs)) return; + /* check for AArch32 CP15DMB/CP15DSB/CP15ISB */ + if (!aarch32_cp15_barriers(regs)) + return; + if (show_unhandled_signals && unhandled_signal(current, SIGILL) && printk_ratelimit()) { pr_info("%s[%d]: undefined instruction: pc=%p\n",