From patchwork Tue Nov 12 13:48:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3172411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 374A99F39E for ; Tue, 12 Nov 2013 13:49:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6C2A620490 for ; Tue, 12 Nov 2013 13:49:51 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B1D1204A2 for ; Tue, 12 Nov 2013 13:49:46 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEKr-0005CX-3y; Tue, 12 Nov 2013 13:48:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEKf-0005nd-Jy; Tue, 12 Nov 2013 13:48:41 +0000 Received: from mail-wi0-f181.google.com ([209.85.212.181]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEKS-0005jy-Em for linux-arm-kernel@lists.infradead.org; Tue, 12 Nov 2013 13:48:34 +0000 Received: by mail-wi0-f181.google.com with SMTP id f4so15432wiw.14 for ; Tue, 12 Nov 2013 05:48:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fUGApTp+GQAAO94yDoQEPDfOtan6RSper2Cdy1UkS8w=; b=HiwgGH7VAKm31t4VFMarcFxue2kVBB9gMJGrE1EsODOeVbzrwr/OU/G1fUQlm6BJvG C129TmAsNVDST2FIGXIxBOrXr9tO7oEbFJ/lmPS/ggv0d5iSj+9/F3fqxWLn7g4t03y5 HcSiP2rYbgN9Fu/FWdD/5taNWmHjePJ6w0RA4HHP43H+0+FtJs4nL+K1pwV4b1IYadbP xydDCJfxR1O73qmJDtQiez/4Jq0822ZVMlSkTFFTD+E0jCu15+XEqCorowhP400+62qr tW/dbcp+E7fTkzP4Cr9jFt2zJNqM2UIX72WsNN/34n+BMVG96m4BvdDGfR4KhaQwm9c2 o2KQ== X-Gm-Message-State: ALoCoQkGAiJdF/b0LhGG0qxK7EtYjYglMY6ERsm427tJQxqV9DZLEMiMAsPn8s4Dv3T/fx/1Y44d X-Received: by 10.180.211.71 with SMTP id na7mr16637374wic.5.1384264089403; Tue, 12 Nov 2013 05:48:09 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id mw9sm45662018wib.0.2013.11.12.05.48.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2013 05:48:08 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH 2/7] ARM: sa1100: use an irqdomain for the high GPIO IRQs Date: Tue, 12 Nov 2013 14:48:05 +0100 Message-Id: <1384264085-6249-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131112_084828_683256_4F744F11 X-CRM114-Status: GOOD ( 15.96 ) X-Spam-Score: -2.6 (--) Cc: Dmitry Eremin-Solenikov , Dmitry Eremin-Solenikov , Dmitry Artamonow , Andrea Adami , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This moves the remaining high GPIO IRQs over to be mapped using a legacy IRQ domain. Signed-off-by: Linus Walleij --- arch/arm/mach-sa1100/irq.c | 47 +++++++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 15fd8a580391..ac032c84763c 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -170,15 +170,6 @@ static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) return 0; } -static struct irq_chip sa1100_high_gpio_chip = { - .name = "GPIO-h", - .irq_ack = sa1100_high_gpio_ack, - .irq_mask = sa1100_high_gpio_mask, - .irq_unmask = sa1100_high_gpio_unmask, - .irq_set_type = sa1100_gpio_type, - .irq_set_wake = sa1100_high_gpio_wake, -}; - /* * We don't need to ACK IRQs on the SA1100 unless they're GPIOs * this is for internal IRQs i.e. from 11 to 31. @@ -213,11 +204,16 @@ static int sa1100_set_wake(struct irq_data *d, unsigned int on) * @domain: irqdomain used to map the irqs for these chips * @low_gpio_chip: irqchip to handle hardware IRQs 0-10 * @normal_chip: irqchip to handle hardware IRQs 12-31 + * @high_domain: irqdomain for the high GPIO IRQs + * @high_gpio_chip: irqchip handling the cascaded IRQs off + * IRQ 11 on the normal chip. */ struct sa1100_sc { struct irq_domain *domain; struct irq_chip low_gpio_chip; struct irq_chip normal_chip; + struct irq_domain *high_domain; + struct irq_chip high_gpio_chip; }; static struct sa1100_sc sa1100_sc = { @@ -236,6 +232,14 @@ static struct sa1100_sc sa1100_sc = { .irq_unmask = sa1100_unmask_irq, .irq_set_wake = sa1100_set_wake, }, + .high_gpio_chip = { + .name = "GPIO-h", + .irq_ack = sa1100_high_gpio_ack, + .irq_mask = sa1100_high_gpio_mask, + .irq_unmask = sa1100_high_gpio_unmask, + .irq_set_type = sa1100_gpio_type, + .irq_set_wake = sa1100_high_gpio_wake, + }, }; asmlinkage void __exception_irq_entry sa1100_handle_irq(struct pt_regs *regs) @@ -266,6 +270,7 @@ static int sa1100_sc_irqdomain_map(struct irq_domain *d, unsigned int irq, if (hwirq >= 12 && hwirq <= 31) irq_set_chip_and_handler(irq, &sc->normal_chip, handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); return 0; } @@ -275,6 +280,22 @@ static struct irq_domain_ops sa1100_sc_irqdomain_ops = { .xlate = irq_domain_xlate_onetwocell, }; +static int sa1100_sc_high_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct sa1100_sc *sc = d->host_data; + + irq_set_chip_data(irq, sc); + irq_set_chip_and_handler(irq, &sc->high_gpio_chip, + handle_edge_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + return 0; +} + +static struct irq_domain_ops sa1100_sc_high_irqdomain_ops = { + .map = sa1100_sc_high_irqdomain_map, + .xlate = irq_domain_xlate_onetwocell, +}; static struct resource irq_resource = DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); @@ -346,7 +367,6 @@ device_initcall(sa1100irq_init_devicefs); void __init sa1100_init_irq(void) { - unsigned int irq; struct sa1100_sc *sc = &sa1100_sc; request_resource(&iomem_resource, &irq_resource); @@ -371,10 +391,7 @@ void __init sa1100_init_irq(void) /* Register IRQs 0-31 using a legacy irqdomain */ sc->domain = irq_domain_add_legacy(NULL, 32, 0, 0, &sa1100_sc_irqdomain_ops, sc); - for (irq = 32; irq <= 48; irq++) { - irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, - handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } + sc->high_domain = irq_domain_add_legacy(NULL, 17, 32, 0, + &sa1100_sc_high_irqdomain_ops, sc); sa1100_init_gpio(); }