From patchwork Tue Nov 12 13:48:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3172431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 177D6C045B for ; Tue, 12 Nov 2013 13:51:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D7D5520490 for ; Tue, 12 Nov 2013 13:51:18 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 084AF20429 for ; Tue, 12 Nov 2013 13:51:14 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgELU-0005U3-4j; Tue, 12 Nov 2013 13:49:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEL1-0005qt-NT; Tue, 12 Nov 2013 13:49:03 +0000 Received: from mail-we0-f174.google.com ([74.125.82.174]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEKl-0005kj-1H for linux-arm-kernel@lists.infradead.org; Tue, 12 Nov 2013 13:48:48 +0000 Received: by mail-we0-f174.google.com with SMTP id t61so640991wes.5 for ; Tue, 12 Nov 2013 05:48:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=cHIkIllYLlV7owLzK6nk0wXuIp3dARBZ+8Zl3B06Z/I=; b=GdPB1pUXuzplcTCg9YhgzIVDTykJu3tL5iDhkWI73Xf8SzueheTSPsyDJpECjuGdNT ts+ibYxsRvgT9MEN9vKswNjjnj8cUbhUCtCHOz7QDHK8/X1yymlP3aQGOs7dyfFXfi5P 9dd8eIpY8SK0/WV4fIcopeGpIBMI4MEFY/gjZneAOQhXNhaOa2kqyngY+cj9e4wlIP1h B56uPU2f60s1LTNu5qbOrR8CwqYnLX/beQxPjik8ow5+p7+QAe27yEP7IlddlkodqxSl GTCyspov7BEL2n42aGnzFvEF+CkXg+hp4aP7H/fDlf5rzMBL5RDwpWRtm2nigHLVjlik jIHw== X-Gm-Message-State: ALoCoQny3Ad01g+ryWZGhRLm9GpSCFB9UPOTTUFOiWaK00fWVFpHAEpEJxGJVqz3D5A68Bi61GI+ X-Received: by 10.180.221.67 with SMTP id qc3mr16533207wic.14.1384264105050; Tue, 12 Nov 2013 05:48:25 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ft19sm44718724wic.5.2013.11.12.05.48.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2013 05:48:24 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH 4/7] ARM: sa1100: use hardware IRQ bit masks Date: Tue, 12 Nov 2013 14:48:21 +0100 Message-Id: <1384264101-6326-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131112_084847_232329_44ABCF74 X-CRM114-Status: GOOD ( 14.31 ) X-Spam-Score: -2.6 (--) Cc: Dmitry Eremin-Solenikov , Dmitry Eremin-Solenikov , Dmitry Artamonow , Andrea Adami , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By using the hardware IRQ number, and setting that to offset from 11 for the high GPIOs, we can get this number to match the bit in the GPIO edge control registers for both low and high GPIOs and we can simplify the code a bit. Signed-off-by: Linus Walleij --- arch/arm/mach-sa1100/irq.c | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index bf36b9abfaad..4b1e6bb60e5e 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -36,20 +36,9 @@ static int GPIO_IRQ_rising_edge; static int GPIO_IRQ_falling_edge; static int GPIO_IRQ_mask = (1 << 11) - 1; -/* - * To get the GPIO number from an IRQ number - */ -#define GPIO_11_27_IRQ(i) ((i) - 21) -#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) - static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { - unsigned int mask; - - if (d->irq <= 10) - mask = 1 << d->irq; - else - mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); if (type == IRQ_TYPE_PROBE) { if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) @@ -131,20 +120,19 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) } /* - * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially. - * In addition, the IRQs are all collected up into one bit in the - * interrupt controller registers. + * GPIO 11 thru GPIO 27 IRQs need to be handled specially. + * These all trigger IRQ 11 on the interrupt controller, so we + * need to use the GPIO edge detect status register to see + * which GPIO was firing the IRQ. */ static void sa1100_high_gpio_ack(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); - - GEDR = mask; + GEDR = BIT(d->hwirq); } static void sa1100_high_gpio_mask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); GPIO_IRQ_mask &= ~mask; @@ -154,7 +142,7 @@ static void sa1100_high_gpio_mask(struct irq_data *d) static void sa1100_high_gpio_unmask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); GPIO_IRQ_mask |= mask; @@ -165,9 +153,9 @@ static void sa1100_high_gpio_unmask(struct irq_data *d) static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= GPIO11_27_MASK(d->irq); + PWER |= BIT(d->hwirq); else - PWER &= ~GPIO11_27_MASK(d->irq); + PWER &= ~BIT(d->hwirq); return 0; } @@ -392,7 +380,7 @@ void __init sa1100_init_irq(void) /* Register IRQs 0-31 using a legacy irqdomain */ sc->domain = irq_domain_add_legacy(NULL, 32, 0, 0, &sa1100_sc_irqdomain_ops, sc); - sc->high_domain = irq_domain_add_legacy(NULL, 17, 32, 0, + sc->high_domain = irq_domain_add_legacy(NULL, 17, 32, 11, &sa1100_sc_high_irqdomain_ops, sc); sa1100_init_gpio(); }