From patchwork Tue Nov 12 13:48:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3173031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1DBB59F3A0 for ; Tue, 12 Nov 2013 14:47:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E7AB20513 for ; Tue, 12 Nov 2013 14:47:47 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6F9520503 for ; Tue, 12 Nov 2013 14:47:44 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgELx-0005nV-DI; Tue, 12 Nov 2013 13:50:03 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgELN-0005ss-V1; Tue, 12 Nov 2013 13:49:25 +0000 Received: from mail-bk0-f42.google.com ([209.85.214.42]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgEKt-0005nD-Db for linux-arm-kernel@lists.infradead.org; Tue, 12 Nov 2013 13:49:09 +0000 Received: by mail-bk0-f42.google.com with SMTP id w16so2272170bkz.15 for ; Tue, 12 Nov 2013 05:48:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SJGDBqB0gAyk0+zEUaUR526WIbsFA8nN5BVAwRYs1sw=; b=SB3VG7eDQ588FaZ5j17LNhaT83V/BHCFPwV4tJBtTa0QF/5EBXHQu+8qfPHtvl8N2P bH4jIg6N7XXIV8ZfClrcE/3/lJSnTP6OJMpB/F8xarLnr12Zoxw91RiFrcJtj3arIrkc gI+H1Ou7PkjY0/R1VhBxHr2/NKgActRAktn4WvMJr+U4NSzypuK0TBoAzVZ6rZSTuIL5 hU8mB3cydIzWKXnj4HOwiEDBCFn9kwBjLHApV6tOeL4INxVkM33fT7kAq7IIfnjxdr2a OP+7yWn4SRH7YyiBmRoAgutUGS+EcsWu3nVWsdEN7lUVFVoiRsFTW+5/fYnQcw8CsYaY TROA== X-Gm-Message-State: ALoCoQlo/qBCeiJAy0ymMqoo0tvwWutdeLUz5QISHZv74QF3zibMQwFdwq3UQzdiNqz1GpfxLaz3 X-Received: by 10.205.24.131 with SMTP id re3mr25821857bkb.8.1384264113200; Tue, 12 Nov 2013 05:48:33 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id pn6sm18256711bkb.14.2013.11.12.05.48.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2013 05:48:32 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH 5/7] ARM: sa1100: move GPIO masks to state container Date: Tue, 12 Nov 2013 14:48:29 +0100 Message-Id: <1384264109-6361-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131112_084855_777560_D0A1832F X-CRM114-Status: GOOD ( 19.68 ) X-Spam-Score: -2.6 (--) Cc: Dmitry Eremin-Solenikov , Dmitry Eremin-Solenikov , Dmitry Artamonow , Andrea Adami , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the masks for the GPIO edges into the SC state container so that we can get rid of the file-local variables. Define the default-on mask for GPIOs 0 thru 11 by a hex value instead of BIT(11) - 1 as the inverse of this hex value is used in the sa1100_high_gpio_handler() function. Signed-off-by: Linus Walleij --- arch/arm/mach-sa1100/irq.c | 98 +++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 4b1e6bb60e5e..5463ba521ac7 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -27,36 +27,53 @@ #include "generic.h" -/* - * SA1100 GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * Use this instead of directly setting GRER/GFER. +/** + * struct sa1100_sc - SA1100 interrupt controller + * @domain: irqdomain used to map the irqs for these chips + * @low_gpio_chip: irqchip to handle hardware IRQs 0-10 + * @normal_chip: irqchip to handle hardware IRQs 12-31 + * @high_domain: irqdomain for the high GPIO IRQs + * @high_gpio_chip: irqchip handling the cascaded IRQs off + * IRQ 11 on the normal chip. + * @gpio_rising: whether the IRQ for the GPIO corresponding to the + * bit in this word should trigger on rising edges. + * @gpio_falling: whether the IRQ for the GPIO corresponding to the + * bit in this word should trigger on falling edges. + * @gpio_mask: whether this GPIO is masked off. */ -static int GPIO_IRQ_rising_edge; -static int GPIO_IRQ_falling_edge; -static int GPIO_IRQ_mask = (1 << 11) - 1; +struct sa1100_sc { + struct irq_domain *domain; + struct irq_chip low_gpio_chip; + struct irq_chip normal_chip; + struct irq_domain *high_domain; + struct irq_chip high_gpio_chip; + u32 gpio_rising; + u32 gpio_falling; + u32 gpio_mask; +}; static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); if (type == IRQ_TYPE_PROBE) { - if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) + if ((sc->gpio_rising | sc->gpio_falling) & mask) return 0; type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } - if (type & IRQ_TYPE_EDGE_RISING) { - GPIO_IRQ_rising_edge |= mask; - } else - GPIO_IRQ_rising_edge &= ~mask; - if (type & IRQ_TYPE_EDGE_FALLING) { - GPIO_IRQ_falling_edge |= mask; - } else - GPIO_IRQ_falling_edge &= ~mask; + if (type & IRQ_TYPE_EDGE_RISING) + sc->gpio_rising |= mask; + else + sc->gpio_rising &= ~mask; + if (type & IRQ_TYPE_EDGE_FALLING) + sc->gpio_falling |= mask; + else + sc->gpio_falling &= ~mask; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; return 0; } @@ -132,22 +149,23 @@ static void sa1100_high_gpio_ack(struct irq_data *d) static void sa1100_high_gpio_mask(struct irq_data *d) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); - GPIO_IRQ_mask &= ~mask; - + sc->gpio_mask &= ~mask; GRER &= ~mask; GFER &= ~mask; } static void sa1100_high_gpio_unmask(struct irq_data *d) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); - GPIO_IRQ_mask |= mask; + sc->gpio_mask |= mask; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; } static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) @@ -188,23 +206,6 @@ static int sa1100_set_wake(struct irq_data *d, unsigned int on) return -EINVAL; } -/** - * struct sa1100_sc - SA1100 interrupt controller - * @domain: irqdomain used to map the irqs for these chips - * @low_gpio_chip: irqchip to handle hardware IRQs 0-10 - * @normal_chip: irqchip to handle hardware IRQs 12-31 - * @high_domain: irqdomain for the high GPIO IRQs - * @high_gpio_chip: irqchip handling the cascaded IRQs off - * IRQ 11 on the normal chip. - */ -struct sa1100_sc { - struct irq_domain *domain; - struct irq_chip low_gpio_chip; - struct irq_chip normal_chip; - struct irq_domain *high_domain; - struct irq_chip high_gpio_chip; -}; - static struct sa1100_sc sa1100_sc = { .low_gpio_chip = { .name = "GPIO-l", @@ -229,6 +230,13 @@ static struct sa1100_sc sa1100_sc = { .irq_set_type = sa1100_gpio_type, .irq_set_wake = sa1100_high_gpio_wake, }, + /* + * This will enable IRQ on GPIOs 0 thru 11 by default, so + * that they always fall through to the normal IRQ controller + * where they can be masked on/off using that IRQ controllers + * mask operations. + */ + .gpio_mask = 0x000007ff, }; asmlinkage void __exception_irq_entry sa1100_handle_irq(struct pt_regs *regs) @@ -298,6 +306,7 @@ static struct sa1100irq_state { static int sa1100irq_suspend(void) { + struct sa1100_sc *sc = &sa1100_sc; struct sa1100irq_state *st = &sa1100irq_state; st->saved = 1; @@ -315,8 +324,8 @@ static int sa1100irq_suspend(void) /* * Set the appropriate edges for wakeup. */ - GRER = PWER & GPIO_IRQ_rising_edge; - GFER = PWER & GPIO_IRQ_falling_edge; + GRER = PWER & sc->gpio_rising; + GFER = PWER & sc->gpio_falling; /* * Clear any pending GPIO interrupts. @@ -328,14 +337,15 @@ static int sa1100irq_suspend(void) static void sa1100irq_resume(void) { + struct sa1100_sc *sc = &sa1100_sc; struct sa1100irq_state *st = &sa1100irq_state; if (st->saved) { ICCR = st->iccr; ICLR = st->iclr; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; ICMR = st->icmr; }