From patchwork Thu Nov 14 15:20:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 3183021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C61CAC045B for ; Thu, 14 Nov 2013 15:26:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 86BF720120 for ; Thu, 14 Nov 2013 15:26:36 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EC922012C for ; Thu, 14 Nov 2013 15:26:35 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgyoP-0000YW-DN; Thu, 14 Nov 2013 15:26:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgyoM-0003Bt-Vl; Thu, 14 Nov 2013 15:26:27 +0000 Received: from mail-pd0-f176.google.com ([209.85.192.176]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VgyoK-0003B4-Jk for linux-arm-kernel@lists.infradead.org; Thu, 14 Nov 2013 15:26:25 +0000 Received: by mail-pd0-f176.google.com with SMTP id w10so23985pde.21 for ; Thu, 14 Nov 2013 07:26:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=J25f3UB4JmIAShn6icNQ+YZ6v5LUnpxVu3eg3ocgvss=; b=SXQDrAgFBga5uBxHP83WRo3xyPllQ3g01JZqx67sR0eC9tuhFVapD/0Z3R8CoPk+ui qFX/sbrswpq+e3dGw1r/PFoMPy+Dx70En1lKr8zyZrXBpcBz/U1pbyAi4AGmhF2qyqkR hBJVOWmAajg8irwBCgUl9ykTqZtuh3OvttA7KMa8j0nGYhuQ//jy3fSA5wvkE6dDXo6Z PEibAEdMBmGD4ICb5vMGkW04tqpd/1CfQjlig3CtU4sKbxbP0LtMmtyII/07OymS1UL5 yoLhq9cELn1BAy4pTNGl5rOgmBSVk9DfQVNNSEhZy9JJZfl/fz2ZTVbIDzbqk1qz9spm xhpQ== X-Gm-Message-State: ALoCoQlOHhwidiZiVRYK9pc+X3reGc0CLWWpSRjzVCf4ARROz3ZYXKY5tjEvTBpneNO00e+DiuWO X-Received: by 10.66.248.202 with SMTP id yo10mr1791558pac.177.1384442432487; Thu, 14 Nov 2013 07:20:32 -0800 (PST) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id qn1sm37828088pbc.34.2013.11.14.07.20.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 14 Nov 2013 07:20:31 -0800 (PST) From: Anup Patel To: kvmarm@lists.cs.columbia.edu Subject: [PATCH RESEND v4] arm64: KVM: Support X-Gene guest VCPU on APM X-Gene host Date: Thu, 14 Nov 2013 20:50:08 +0530 Message-Id: <1384442408-13286-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131114_102624_718299_44AB5E18 X-CRM114-Status: GOOD ( 12.88 ) X-Spam-Score: -1.9 (-) Cc: linaro-kernel@lists.linaro.org, Anup Patel , patches@linaro.org, Marc Zyngier , Catalin Marinas , Jitendra Kanitkar , Jon Masters , ksankaran@apm.com, linux-arm-kernel , Pranavkumar Sawargaonkar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch allows us to have X-Gene guest VCPU when using KVM arm64 on APM X-Gene host. We add KVM_ARM_TARGET_XGENE_POTENZA for X-Gene Potenza compatible guest VCPU and we return KVM_ARM_TARGET_XGENE_POTENZA in kvm_target_cpu() when running on X-Gene host with Potenza core. V4: - Remove default case from switch statments in kvm_target_cpu() V3: - Reduce multiple "return -EINVAL" in kvm_target_cpu() V2: - Renamed KVM_ARM_TARGET_XGENE_V8 to KVM_ARM_TARGET_XGENE_POTENZA V1: - Initial patch with target named as KVM_ARM_TARGET_XGENE_V8 Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar --- arch/arm64/include/uapi/asm/kvm.h | 3 ++- arch/arm64/kvm/guest.c | 32 +++++++++++++++++++------------- arch/arm64/kvm/sys_regs_generic_v8.c | 3 +++ 3 files changed, 24 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 5031f42..d9f026b 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -55,8 +55,9 @@ struct kvm_regs { #define KVM_ARM_TARGET_AEM_V8 0 #define KVM_ARM_TARGET_FOUNDATION_V8 1 #define KVM_ARM_TARGET_CORTEX_A57 2 +#define KVM_ARM_TARGET_XGENE_POTENZA 3 -#define KVM_ARM_NUM_TARGETS 3 +#define KVM_ARM_NUM_TARGETS 4 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ #define KVM_ARM_DEVICE_TYPE_SHIFT 0 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 2c3ff67..d7bf7d6 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -207,20 +207,26 @@ int __attribute_const__ kvm_target_cpu(void) unsigned long implementor = read_cpuid_implementor(); unsigned long part_number = read_cpuid_part_number(); - if (implementor != ARM_CPU_IMP_ARM) - return -EINVAL; + switch (implementor) { + case ARM_CPU_IMP_ARM: + switch (part_number) { + case ARM_CPU_PART_AEM_V8: + return KVM_ARM_TARGET_AEM_V8; + case ARM_CPU_PART_FOUNDATION: + return KVM_ARM_TARGET_FOUNDATION_V8; + case ARM_CPU_PART_CORTEX_A57: + return KVM_ARM_TARGET_CORTEX_A57; + }; + break; + case ARM_CPU_IMP_APM: + switch (part_number) { + case APM_CPU_PART_POTENZA: + return KVM_ARM_TARGET_XGENE_POTENZA; + }; + break; + }; - switch (part_number) { - case ARM_CPU_PART_AEM_V8: - return KVM_ARM_TARGET_AEM_V8; - case ARM_CPU_PART_FOUNDATION: - return KVM_ARM_TARGET_FOUNDATION_V8; - case ARM_CPU_PART_CORTEX_A57: - /* Currently handled by the generic backend */ - return KVM_ARM_TARGET_CORTEX_A57; - default: - return -EINVAL; - } + return -EINVAL; } int kvm_vcpu_set_target(struct kvm_vcpu *vcpu, diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c index 4268ab9..8fe6f76 100644 --- a/arch/arm64/kvm/sys_regs_generic_v8.c +++ b/arch/arm64/kvm/sys_regs_generic_v8.c @@ -90,6 +90,9 @@ static int __init sys_reg_genericv8_init(void) &genericv8_target_table); kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A57, &genericv8_target_table); + kvm_register_target_sys_reg_table(KVM_ARM_TARGET_XGENE_POTENZA, + &genericv8_target_table); + return 0; } late_initcall(sys_reg_genericv8_init);