[v3,2/4] Documentation: Add documentation for APM X-Gene SATA controllor DTS binding

Commit Message

Loc Ho Nov. 14, 2013, 9:39 p.m. UTC

Documentation:: Add documentation for APM X-Gene SoC SATA host controller DTS binding

Signed-off-by: Loc Ho <[e-mail]>
Signed-off-by: Tuan Phan <[e-mail]>
Signed-off-by: Suman Tripathi <[e-mail]>
Reviewed-by: Arnd Bergmann <[e-mail]>
Reviewed-by: Olof Johansson <[e-mail]>
---
 .../devicetree/bindings/ata/apm-xgene.txt          |   62 +++++++++++++++++++-
 1 files changed, 61 insertions(+), 1 deletions(-)

Comments

Arnd Bergmann Nov. 15, 2013, 1:28 p.m. UTC | #1

On Thursday 14 November 2013, Loc Ho wrote:
> +Required properties:
> +- compatible           : Shall be "apm,xgene-ahci"
> +- reg                  : First memory resource shall be the AHCI memory
> +                         resource.
> +                         Second memory resource shall be the host controller
> +                         memory resource.
> +- id                   : Controller ID (0 = first, 1 = second, 2 = third)

As in the PHY patch, it's probably best to drop the "id" property here and
describe the actual differences between the instances directly, either by
having distinct "compatible" properties for each model, or by adding binary
flags to tell about a capability that only some instances have.

Also, I think you should have a separate file for the sata binding, especially
since the PHY binding is not actually specific to SATA at all.

Aside from these, the binding looks good to me now.

	Arnd

Patch

diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
index d18db67..0d16bfe 100644
--- a/Documentation/devicetree/bindings/ata/apm-xgene.txt
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -1,4 +1,4 @@ 
-* APM X-Gene 6.0 Gb/s SATA PHY nodes
+* APM X-Gene 6.0 Gb/s SATA PHY and controller nodes
 
 SATA PHY nodes are defined to describe on-chip Serial ATA PHY. Each SATA PHY
 (pair of PHY) has its own node.
@@ -67,3 +67,63 @@  Example:
 			status = "ok";
 		};
 
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible		: Shall be "apm,xgene-ahci"
+- reg			: First memory resource shall be the AHCI memory
+			  resource.
+			  Second memory resource shall be the host controller
+			  memory resource.
+- id			: Controller ID (0 = first, 1 = second, 2 = third)
+- interrupt-parent	: Interrupt controller
+- interrupts		: Interrupt mapping for SATA host controller IRQ
+- clocks		: Reference to the clock entry
+- phys			: PHY reference
+- phy-names		: Name of the PHY reference
+
+Optional properties:
+- status		: Shall be "ok" if enabled or "na" if disabled.
+			  Default is "ok".
+
+Example:
+		sata0: sata@1a000000 {
+			compatible = "apm,xgene-ahci";
+			id = <0>;
+			reg =  <0x0 0x1a000000 0x0 0x100000
+				0x0 0x1f210000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0x0 0x86 0x4>;
+		        clocks = <&eth01clk 0>;
+			status = "na";
+			phys = <&sataphy0>;
+			phy-names = "sataphy0";
+		};
+
+		sata1: sata@1a400000 {
+			compatible = "apm,xgene-ahci";
+			id = <1>;
+			reg =  <0x0 0x1a400000 0x0 0x100000
+				0x0 0x1f220000 0x0 0x10000>;
+			interrupt-parent = <&gic>;
+			interrupts = <0x0 0x87 0x4>;
+		        clocks = <&eth23clk 0>;
+			status = "ok";
+			phys = <&sataphy1>;
+			phy-names = "sataphy1";
+		};
+
+		sata2: sata@1a800000 {
+			compatible = "apm,xgene-ahci";
+			id = <2>;
+			reg =  <0x0 0x1a800000 0x0 0x100000
+				0x0 0x1f230000 0x0 0x10000
+				0x0 0x1f2d0000 0x0 0x10000 >;
+			interrupt-parent = <&gic>;
+			interrupts = <0x0 0x88 0x4>;
+		        clocks = <&sata45clk 0>;
+			status = "ok";
+			phys = <&sataphy2>;
+			phy-names = "sataphy2";
+		};