From patchwork Wed Nov 20 15:46:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 3213591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 13AD8C045B for ; Wed, 20 Nov 2013 15:50:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33E542074C for ; Wed, 20 Nov 2013 15:50:34 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93126200F3 for ; Wed, 20 Nov 2013 15:50:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjA1T-0008Pg-97; Wed, 20 Nov 2013 15:49:00 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjA12-0003o1-Fu; Wed, 20 Nov 2013 15:48:32 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjA0S-0003ix-4I; Wed, 20 Nov 2013 15:47:59 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id rAKFlJiR017312; Wed, 20 Nov 2013 09:47:19 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAKFlIng002571; Wed, 20 Nov 2013 09:47:18 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Wed, 20 Nov 2013 09:47:18 -0600 Received: from uglx0177649.ucm2.emeaucm.ext.ti.com (uglx0177649.ucm2.emeaucm.ext.ti.com [10.167.145.122]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAKFl034003976; Wed, 20 Nov 2013 09:47:14 -0600 From: Ivan Khoronzhuk To: Santosh Shilimkar , Rob Landley , Russell King Subject: [PATCH 2/2] memory: ti-aemif: add bindings for AEMIF driver Date: Wed, 20 Nov 2013 17:46:56 +0200 Message-ID: <1384962416-14862-3-git-send-email-ivan.khoronzhuk@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1384962416-14862-1-git-send-email-ivan.khoronzhuk@ti.com> References: <1384962416-14862-1-git-send-email-ivan.khoronzhuk@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131120_104756_439253_24F87E99 X-CRM114-Status: GOOD ( 17.93 ) X-Spam-Score: -7.5 (-------) Cc: Mark Rutland , devicetree@vger.kernel.org, grygorii.strashko@ti.com, Pawel Moll , Stephen Warren , gregkh@linuxfoundation.org, Ian Campbell , Kumar Gala , Rob Herring , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Ivan Khoronzhuk , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for AEMIF controller drivers/memory/ti-aemif.c Signed-off-by: Ivan Khoronzhuk --- .../bindings/memory-controllers/ti-aemif.txt | 198 ++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt new file mode 100644 index 0000000..be0c0cb --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt @@ -0,0 +1,198 @@ +* Device tree bindings for Texas instruments AEMIF controller + +Th Async External Memory Interface (EMIF16/AEMIF) controller is intended to +provide a glue-less interface to a variety of asynchronous memory devices like +ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories +can be accessed at any given time via four chip selects with 64M byte access +per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM +and Mobile SDR are not supported. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf +OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf +Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf + +Required properties: + +- compatible: "ti,davinci-aemif" + "ti,keystone-aemif" + "ti,omap-L138-aemif" + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be set to 1. + +- reg: contains offset/length value for AEMIF control registers + space. + +- ranges: Must be set up to reflect the memory layout for 4 + chipselects and for AEMIF control range. + +- clocks: phandle reference to the controller clock. Required only + if clock tree data present in device tree. + See clock-bindings.txt + +- clock-names: clock name. It has to be "aemif". Required only if clock + tree data present in device tree, in another case don't + use it. + See clock-bindings.txt + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + See clock-bindings.txt + + +Child chip-select (cs) nodes contain the memory devices nodes connected to +such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt). +There might be board specific devices like FPGAs. + +Required child cs node properties: + +- compatible: "ti,aemif-cs" + +- #address-cells: Must be 2. The first cell is the memory partition + number. The 0 partition is for chip selects. And the + second cell is the offset into the partition, for the 0 + partition it corresponds to chip select offset. + +- #size-cells: Must be 1. + +- ranges: Empty property indicating that child nodes can inherit + memory layout. + +- clock-ranges: Empty property indicating that child nodes can inherit + named clocks. Required only if clock tree data present + in device tree. + +Optional child cs node properties: + + +- ti,bus-width: width of the asynchronous device's data bus + 8 or 16 if not preset 8 + +- ti,cs-ss: enable/disable select strobe mode + In select strobe mode chip select behaves as + the strobe and is active only during the strobe + period. If present then enable. + +- ti,cs-ew: enable/disable extended wait mode + if set, the controller monitors the EMIFWAIT pin + mapped to that chip select to determine if the + device wants to extend the strobe period. If + present then enable. + +- ti,cs-ta: minimum turn around time, ns + Time between the end of one asynchronous memory + access and the start of another asynchronous + memory access. This delay is not incurred + between a read followed by read or a write + followed by a write to same chip select. + +- ti,cs-rsetup: read setup width, ns + Time between the beginning of a memory cycle + and the activation of read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rstobe: read strobe width, ns + Time between the activation and deactivation of + the read strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-rhold: read hold width, ns + Time between the deactivation of the read + strobe and the end of the cycle (which may be + either an address change or the deactivation of + the chip select signal. + Minimum value is 1 (0 treated as 1). + +- ti,cs-wsetup: write setup width, ns + Time between the beginning of a memory cycle + and the activation of write strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-wstrobe: write strobe width, ns + Time between the activation and deactivation of + the write strobe. + Minimum value is 1 (0 treated as 1). + +- ti,cs-whold: write hold width, ns + Time between the deactivation of the write + strobe and the end of the cycle (which may be + either an address change or the deactivation of + the chip select signal. + Minimum value is 1 (0 treated as 1). + +If any of the above parameters are absent, current parameter value will be taken +from the corresponding HW reg. + +The name for cs node must be in format csN, where N is the cs number. +For compatibles "ti,davinci-aemif" and "ti,keystone-aemif" N = [0-3]. +For compatible "ti,omap-L138-aemif" N = [2-5]. + +Example for aemif, davinci nand and nor flash chip select shown below. + +memory-controller@21000A00 { + compatible = "ti,keystone-aemif"; + #address-cells = <2>; + #size-cells = <1>; + clocks = <&clkaemif 0>; + clock-names = "aemif"; + clock-ranges; + reg = <0x2100A00 0x00000100>; + ranges = <0 0 0x70000000 0x10000000 + 1 0 0x21000A00 0x0000100>; + + nand:cs2 { + compatible = "ti,aemif-cs"; + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + /* all timings in nanoseconds */ + ti,cs-ta = <0>; + ti,cs-rhold = <7>; + ti,cs-rstrobe = <42>; + ti,cs-rsetup = <14>; + ti,cs-whold = <7>; + ti,cs-wstrobe = <42>; + ti,cs-wsetup = <14>; + + nand@0,0x8000000 { + compatible = "ti,davinci-nand"; + reg = <0 0x8000000 0x4000000 + 1 0x0000000 0x0000100>; + + .. see davinci-nand.txt + }; + }; + + nor:cs0 { + compatible = "ti,aemif-cs"; + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + /* all timings in nanoseconds */ + ti,cs-ta = <0>; + ti,cs-rhold = <8>; + ti,cs-rstrobe = <40>; + ti,cs-rsetup = <14>; + ti,cs-whold = <7>; + ti,cs-wstrobe = <40>; + ti,cs-wsetup = <14>; + ti,cs-asize = <1>; + + flash@0,0x0000000 { + compatible = "cfi-flash"; + reg = <0 0x0000000 0x4000000>; + + ... + }; + }; +};