From patchwork Wed Nov 20 16:24:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 3213661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 25327C045B for ; Wed, 20 Nov 2013 16:28:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 048E12075F for ; Wed, 20 Nov 2013 16:28:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3A5D20761 for ; Wed, 20 Nov 2013 16:28:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjAc8-0001lE-F3; Wed, 20 Nov 2013 16:26:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjAbl-0005iG-VB; Wed, 20 Nov 2013 16:26:29 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjAbA-0005bp-71; Wed, 20 Nov 2013 16:25:54 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id rAKGPHd4022280; Wed, 20 Nov 2013 10:25:17 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAKGPGRA030723; Wed, 20 Nov 2013 10:25:16 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 20 Nov 2013 10:25:15 -0600 Received: from uglx0177649.ucm2.emeaucm.ext.ti.com (uglx0177649.ucm2.emeaucm.ext.ti.com [10.167.145.122]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rAKGP3qS002299; Wed, 20 Nov 2013 10:25:12 -0600 From: Ivan Khoronzhuk To: Santosh Shilimkar , Rob Landley , Russell King Subject: [PATCH 2/3] mtd: nand: davinci: don't set timings if AEMIF is used Date: Wed, 20 Nov 2013 18:24:58 +0200 Message-ID: <1384964699-15134-3-git-send-email-ivan.khoronzhuk@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1384964699-15134-1-git-send-email-ivan.khoronzhuk@ti.com> References: <1384964699-15134-1-git-send-email-ivan.khoronzhuk@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131120_112552_463603_6E9DE267 X-CRM114-Status: GOOD ( 17.48 ) X-Spam-Score: -7.5 (-------) Cc: Mark Rutland , devicetree@vger.kernel.org, grygorii.strashko@ti.com, Pawel Moll , Stephen Warren , Ian Campbell , Kumar Gala , Rob Herring , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Ivan Khoronzhuk , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The problem that the set timings code contains the call of Davinci platform function davinci_aemif_setup_timing() which is not accessible if kernel is built for Keystone only. The Keysone platform is going to use TI AEMIF driver. If TI AEMIF is used we don't need to set timings and bus width. It is done by AEMIF driver (drivers/memory/ti-aemfi.c). The timings code has to be removed together with Davinci aemif platform code (aemif.c), once Davinci will be converted to DT and use ti-aemif.c driver. Signed-off-by: Ivan Khoronzhuk --- drivers/mtd/nand/davinci_nand.c | 48 +++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 8459720..e904364 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -605,6 +605,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev) int ret; uint32_t val; nand_ecc_modes_t ecc_mode; + bool aemif = IS_ENABLED(CONFIG_TI_AEMIF); pdata = nand_davinci_get_pdata(pdev); if (IS_ERR(pdata)) @@ -741,25 +742,38 @@ static int __init nand_davinci_probe(struct platform_device *pdev) } /* - * Setup Async configuration register in case we did not boot from - * NAND and so bootloader did not bother to set it up. + * TODO: + * This is temp solution to support Davinci platform and it has to be + * removed once Davinci will be updated to use ti-aemif.c driver. */ - val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4); - - /* Extended Wait is not valid and Select Strobe mode is not used */ - val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); - if (info->chip.options & NAND_BUSWIDTH_16) - val |= 0x1; - - davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val); + if (!aemif) { + /* + * Setup Async configuration register in case we did not boot + * from NAND and so bootloader did not bother to set it up. + */ + val = davinci_nand_readl(info, A1CR_OFFSET + + info->core_chipsel * 4); - ret = 0; - if (info->timing) - ret = davinci_aemif_setup_timing(info->timing, info->base, - info->core_chipsel); - if (ret < 0) { - dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); - goto err; + /* + * Extended Wait is not valid and Select Strobe mode is not + * used + */ + val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); + if (info->chip.options & NAND_BUSWIDTH_16) + val |= 0x1; + + davinci_nand_writel(info, A1CR_OFFSET + + info->core_chipsel * 4, val); + + ret = 0; + if (info->timing) + ret = davinci_aemif_setup_timing(info->timing, + info->base, + info->core_chipsel); + if (ret < 0) { + dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); + goto err; + } } spin_lock_irq(&davinci_nand_lock);