| Message ID | 1384991242-13596-1-git-send-email-swarren@wwwdotorg.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Nov 21, 2013 at 12:47:18AM +0100, Stephen Warren wrote: > From: Stephen Warren <swarren@nvidia.com> > > The blink clock rate needs to be configured, or it will run at ~1Hz > rather than the desired 32KHz. If it runs at the wrong rate, e.g. the > SDIO WiFi on Seaboard and Cardhu will fail to be detected. > > Signed-off-by: Stephen Warren <swarren@nvidia.com> > --- > This probably needs to be squashed into commit 32721a734a3d "clk: tegra: > move PMC, fixed clocks to common files". > --- Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> I will squash this into the mentioned commit. Cheers, Peter.
On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote: > From: Stephen Warren <swarren@nvidia.com> > > The blink clock rate needs to be configured, or it will run at ~1Hz > rather than the desired 32KHz. If it runs at the wrong rate, e.g. the > SDIO WiFi on Seaboard and Cardhu will fail to be detected. How is this related to WiFi? > > Signed-off-by: Stephen Warren <swarren@nvidia.com> > --- > This probably needs to be squashed into commit 32721a734a3d "clk: tegra: > move PMC, fixed clocks to common files". > --- > drivers/clk/tegra/clk-tegra-pmc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c > index 00e8275a7178..08b21c1ee867 100644 > --- a/drivers/clk/tegra/clk-tegra-pmc.c > +++ b/drivers/clk/tegra/clk-tegra-pmc.c > @@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base, > } > > /* blink */ > + writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); > clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, > pmc_base + PMC_DPD_PADS_ORIDE, > PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); Perhaps a better location would be a few lines below, where the "blink" clock is registered, since this actually controls the "blink" clock rather than "blink_override". But either way: Reviewed-by: Thierry Reding <treding@nvidia.com>
On Fri, Nov 29, 2013 at 04:22:42PM +0100, Thierry Reding wrote: > On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote: > > From: Stephen Warren <swarren@nvidia.com> > > > > The blink clock rate needs to be configured, or it will run at ~1Hz > > rather than the desired 32KHz. If it runs at the wrong rate, e.g. the > > SDIO WiFi on Seaboard and Cardhu will fail to be detected. > > How is this related to WiFi? > > > > > Signed-off-by: Stephen Warren <swarren@nvidia.com> > > --- > > This probably needs to be squashed into commit 32721a734a3d "clk: tegra: > > move PMC, fixed clocks to common files". > > --- > > drivers/clk/tegra/clk-tegra-pmc.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c > > index 00e8275a7178..08b21c1ee867 100644 > > --- a/drivers/clk/tegra/clk-tegra-pmc.c > > +++ b/drivers/clk/tegra/clk-tegra-pmc.c > > @@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base, > > } > > > > /* blink */ > > + writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); > > clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, > > pmc_base + PMC_DPD_PADS_ORIDE, > > PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); > > Perhaps a better location would be a few lines below, where the "blink" > clock is registered, since this actually controls the "blink" clock > rather than "blink_override". But either way: Just realized that Peter already squashed all of these into his -next branch, so nevermind. Thierry
On 11/29/2013 08:22 AM, Thierry Reding wrote: > On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote: >> From: Stephen Warren <swarren@nvidia.com> >> >> The blink clock rate needs to be configured, or it will run at >> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate, >> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be >> detected. > > How is this related to WiFi? The "blink" clock output from Tegra is connected to the WiFi module, which then uses it for something; it probably has a PLL connected to it that drives all the internal circuitry.
On Sun, Dec 01, 2013 at 12:21:17PM -0700, Stephen Warren wrote: > On 11/29/2013 08:22 AM, Thierry Reding wrote: > > On Wed, Nov 20, 2013 at 04:47:18PM -0700, Stephen Warren wrote: > >> From: Stephen Warren <swarren@nvidia.com> > >> > >> The blink clock rate needs to be configured, or it will run at > >> ~1Hz rather than the desired 32KHz. If it runs at the wrong rate, > >> e.g. the SDIO WiFi on Seaboard and Cardhu will fail to be > >> detected. > > > > How is this related to WiFi? > > The "blink" clock output from Tegra is connected to the WiFi module, > which then uses it for something; it probably has a PLL connected to > it that drives all the internal circuitry. Okay, thanks for explaining. Thierry
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 00e8275a7178..08b21c1ee867 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -114,6 +114,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base, } /* blink */ + writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, pmc_base + PMC_DPD_PADS_ORIDE, PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);