From patchwork Thu Nov 21 18:15:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 3220121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BC8A59F461 for ; Thu, 21 Nov 2013 18:17:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8B128206CE for ; Thu, 21 Nov 2013 18:17:04 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C3E120635 for ; Thu, 21 Nov 2013 18:17:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjYnq-0003hp-B4; Thu, 21 Nov 2013 18:16:34 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjYng-0002R8-Gy; Thu, 21 Nov 2013 18:16:24 +0000 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjYnY-0002OH-0F for linux-arm-kernel@lists.infradead.org; Thu, 21 Nov 2013 18:16:18 +0000 Received: by mail-pa0-f53.google.com with SMTP id hz1so109881pad.12 for ; Thu, 21 Nov 2013 10:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T9KZdM5bz+Dc5Zc7xquMxhc+1/HQnaDxBZm3A24YSko=; b=Q1TScb2CdBbV4ctMdou4lsloL/JylMEGrCvR6peIUbY8sw0ANDwLqedVEjk5i/WnrX aZDJq5nogBcUIQ4Xz4zr0FqpM8/EivNbaSjDSYvRKy2UUbJhOfhsO2ULatGDgRndlCKt cIgBm87koiumd5TbvP2ppm5pZI91Auc7H6CXyIKiz5ewoTSBUOKnJXeOBMxCVi0BtqeT RyjCam3cwUh4tVh4FumATzfFMy0N6H3YJkPwRY2GxzSCuhxVTiTrMIyR7A8De2htJmYZ jT8kvoou+uLEa9U75Rfx1u1zYQTV47EWDk+ZFLS1g2gsig6/8hwHqU6G8YjIQPvHhIAY e9Rg== X-Received: by 10.68.59.202 with SMTP id b10mr7834749pbr.78.1385057754389; Thu, 21 Nov 2013 10:15:54 -0800 (PST) Received: from localhost.localdomain ([59.161.53.225]) by mx.google.com with ESMTPSA id bl8sm43648678pad.17.2013.11.21.10.15.46 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 21 Nov 2013 10:15:53 -0800 (PST) From: Prabhakar Lad To: Sekhar Nori , Linus Walleij , Grygorii Strashko Subject: [PATCH v6 1/6] gpio: davinci: use readl/writel instead of __raw_* Date: Thu, 21 Nov 2013 23:45:26 +0530 Message-Id: <1385057731-4348-2-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1385057731-4348-1-git-send-email-prabhakar.csengg@gmail.com> References: <1385057731-4348-1-git-send-email-prabhakar.csengg@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131121_131616_443504_8CA21BB3 X-CRM114-Status: GOOD ( 16.14 ) X-Spam-Score: -2.0 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, DLOS , Pawel Moll , linux-doc@vger.kernel.org, Stephen Warren , LKML , Rob Herring , linux-gpio@vger.kernel.org, Prabhakar Lad , Rob Landley , Grant Likely , Ian Campbell , LAK X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Lad, Prabhakar" This patch replaces the __raw_readl/writel with readl and writel, Altough the code runs on ARMv5 based SOCs, changing this will help copying the code for other uses. Acked-by: Linus Walleij Signed-off-by: Lad, Prabhakar --- drivers/gpio/gpio-davinci.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 84be701..1f33fcd 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -82,14 +82,14 @@ static inline int __davinci_direction(struct gpio_chip *chip, u32 mask = 1 << offset; spin_lock_irqsave(&d->lock, flags); - temp = __raw_readl(&g->dir); + temp = readl(&g->dir); if (out) { temp &= ~mask; - __raw_writel(mask, value ? &g->set_data : &g->clr_data); + writel(mask, value ? &g->set_data : &g->clr_data); } else { temp |= mask; } - __raw_writel(temp, &g->dir); + writel(temp, &g->dir); spin_unlock_irqrestore(&d->lock, flags); return 0; @@ -118,7 +118,7 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; - return (1 << offset) & __raw_readl(&g->in_data); + return (1 << offset) & readl(&g->in_data); } /* @@ -130,7 +130,7 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; - __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); + writel((1 << offset), value ? &g->set_data : &g->clr_data); } static int davinci_gpio_probe(struct platform_device *pdev) @@ -227,8 +227,8 @@ static void gpio_irq_disable(struct irq_data *d) struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); u32 mask = (u32) irq_data_get_irq_handler_data(d); - __raw_writel(mask, &g->clr_falling); - __raw_writel(mask, &g->clr_rising); + writel(mask, &g->clr_falling); + writel(mask, &g->clr_rising); } static void gpio_irq_enable(struct irq_data *d) @@ -242,9 +242,9 @@ static void gpio_irq_enable(struct irq_data *d) status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (status & IRQ_TYPE_EDGE_FALLING) - __raw_writel(mask, &g->set_falling); + writel(mask, &g->set_falling); if (status & IRQ_TYPE_EDGE_RISING) - __raw_writel(mask, &g->set_rising); + writel(mask, &g->set_rising); } static int gpio_irq_type(struct irq_data *d, unsigned trigger) @@ -286,10 +286,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) int res; /* ack any irqs */ - status = __raw_readl(&g->intstat) & mask; + status = readl(&g->intstat) & mask; if (!status) break; - __raw_writel(status, &g->intstat); + writel(status, &g->intstat); /* now demux them to the right lowlevel handler */ n = d->irq_base; @@ -346,9 +346,9 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) ? &g->set_rising : &g->clr_rising); return 0; @@ -432,8 +432,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) /* default trigger: both edges */ g = gpio2regs(0); - __raw_writel(~0, &g->set_falling); - __raw_writel(~0, &g->set_rising); + writel(~0, &g->set_falling); + writel(~0, &g->set_rising); /* set the direct IRQs up to use that irqchip */ for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { @@ -456,8 +456,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) /* disabled by default, enabled only as needed */ g = gpio2regs(gpio); - __raw_writel(~0, &g->clr_falling); - __raw_writel(~0, &g->clr_rising); + writel(~0, &g->clr_falling); + writel(~0, &g->clr_rising); /* set up all irqs in this bank */ irq_set_chained_handler(bank_irq, gpio_irq_handler); @@ -485,7 +485,7 @@ done: * BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, gpio_base + BINTEN); + writel(binten, gpio_base + BINTEN); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));