From patchwork Wed Nov 27 15:19:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 3248591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4F6AFC045B for ; Wed, 27 Nov 2013 15:26:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 92BDD205CD for ; Wed, 27 Nov 2013 15:26:27 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BA68205C6 for ; Wed, 27 Nov 2013 15:26:26 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vlh0P-00052n-SJ; Wed, 27 Nov 2013 15:26:22 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vlh0N-00072X-DD; Wed, 27 Nov 2013 15:26:19 +0000 Received: from mail-lb0-f170.google.com ([209.85.217.170]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vlh0K-0006zd-PJ for linux-arm-kernel@lists.infradead.org; Wed, 27 Nov 2013 15:26:17 +0000 Received: by mail-lb0-f170.google.com with SMTP id w7so5597633lbi.29 for ; Wed, 27 Nov 2013 07:25:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=OW+9EHq28kxunbwT6a9UODbK1lnAmTxUPTmm9RNAzYg=; b=GRfsDs/vsK6OsH9R4muRic1CKKOiEnCXLK2FQketR3v27YO3kaKEm4ngVlJ06EFDBd z2Oq9ifxi6maL1FgRloffl9Qgs0Rp4Lh5B9g/IQwl24nfKWCth/dNNLQOUJLTc1TKO4K SRE2k6kJ+A5f0hGzFO83VHHfE31WVp40WBGHkYYsG++ZJ/bogLGsUixumF5XtpKStXj/ 5GYl3sRApc9nbEdWvZ3EOlVUt9lOwZUsya2VICaJS4HUmBW1kgpV/RzOv0fA8oMsvo0j 85zxDDZm9ToixHSOtvTlEy+x9nbMPtLcmC6f6x2E5yXHDfFd1YJeyDiPzPBA9C8zXY+x /zHw== X-Gm-Message-State: ALoCoQm11msZzOhhkiuJBd+vNxMWm2TtayDU2QjtnqPnMTG8vjuf3wX5lJknGC8nZ2KuJLclVkSS X-Received: by 10.112.53.97 with SMTP id a1mr1865054lbp.38.1385565592722; Wed, 27 Nov 2013 07:19:52 -0800 (PST) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id i8sm15507475lbh.2.2013.11.27.07.19.50 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 27 Nov 2013 07:19:51 -0800 (PST) From: Taras Kondratiuk To: Rob Herring Subject: [PATCH v2] ARM: OMAP4/highbank: Flush L2 cache before disabling Date: Wed, 27 Nov 2013 17:19:44 +0200 Message-Id: <1385565585-28306-1-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131127_102616_972954_512DC71C X-CRM114-Status: GOOD ( 14.41 ) X-Spam-Score: -2.6 (--) Cc: linaro-kernel@lists.linaro.org, Russell King , patches@linaro.org, Tony Lindgren , linux-kernel@vger.kernel.org, linaro-networking@linaro.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Kexec disables outer cache before jumping to reboot code, but it doesn't flush it explicitly. Flush is done implicitly inside of l2x0_disable(). But some SoC's override default .disable handler and don't flush cache. This may lead to a corrupted memory during Kexec reboot on these platforms. This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() handlers to make it consistent with default l2x0_disable(). Acked-by: Rob Herring Acked-by: Santosh Shilimkar Acked-by: Tony Lindgren Signed-off-by: Taras Kondratiuk --- I was not aware about Russell's patch tracker process, so this patch was not hooked there. Highbank moved to PSCI since then, so patch has to be slightly modified. Rob, are you still ok with this patch? v1..v2: Removed changes in highbank_suspend_finish since after commit dd68eb0 "ARM: highbank: adapt to use ARM PSCI calls" cache is not explicitly disabled there. v1: http://www.spinics.net/lists/linux-omap/msg98318.html RFC v2: https://patchwork.kernel.org/patch/2990231/ Make the fix specific to platforms that don't use l2x0_disable(). RFC v1: https://patchwork.kernel.org/patch/2974431/ Based on v3.13-rc1 --- arch/arm/mach-highbank/highbank.c | 1 + arch/arm/mach-omap2/omap4-common.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index b3d7e56..ae17150 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c @@ -50,6 +50,7 @@ static void __init highbank_scu_map_io(void) static void highbank_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ highbank_smc1(0x102, 0x0); } diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b39efd4..c0ab9b2 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -162,6 +162,7 @@ void __iomem *omap4_get_l2cache_base(void) static void omap4_l2x0_disable(void) { + outer_flush_all(); /* Disable PL310 L2 Cache controller */ omap_smc1(0x102, 0x0); }