From patchwork Thu Nov 28 07:19:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwenhael Goavec-Merou X-Patchwork-Id: 3252941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 698C79F3A0 for ; Thu, 28 Nov 2013 09:17:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 60A5520348 for ; Thu, 28 Nov 2013 09:17:35 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AD48200E1 for ; Thu, 28 Nov 2013 09:17:34 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VlxiK-00054L-1Z; Thu, 28 Nov 2013 09:16:48 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vlxi8-0006eK-OL; Thu, 28 Nov 2013 09:16:36 +0000 Received: from kmf.trabucayre.com ([91.121.117.161] helo=mail) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vlxho-0006ba-2F for linux-arm-kernel@lists.infradead.org; Thu, 28 Nov 2013 09:16:17 +0000 Received: from localhost.localdomain (localhost [127.0.0.1]) by mail (Postfix) with ESMTP id A7F933983A; Thu, 28 Nov 2013 08:19:33 +0100 (CET) From: Gwenhael Goavec-Merou To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv2 1/3] ARM: imx27: add pingroups for cspi, sdhc and framebuffer Date: Thu, 28 Nov 2013 08:19:30 +0100 Message-Id: <1385623172-87429-1-git-send-email-gwenhael.goavec-merou@armadeus.com> X-Mailer: git-send-email 1.6.4.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131128_041616_255953_A4F8983B X-CRM114-Status: UNSURE ( 8.14 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.2 (-) Cc: devicetree@vger.kernel.org, Sascha Hauer , shawn.guo@linaro.org, Linus Walleij , Gwenhael Goavec-Merou X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Gwenhael Goavec-Merou --- Changelog: v2: * pingroups entries are now sorted alphabetically; * framebuffer pingroup is renamed: MX27_FB1_PINGRP1 -> MX27_FB_PINGRP1 arch/arm/boot/dts/imx27-pingrp.h | 68 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/imx27-pingrp.h b/arch/arm/boot/dts/imx27-pingrp.h index 08d8d18..f3fbf5a 100644 --- a/arch/arm/boot/dts/imx27-pingrp.h +++ b/arch/arm/boot/dts/imx27-pingrp.h @@ -13,6 +13,50 @@ #include "imx27-pinfunc.h" +#define MX27_CSPI1_PINGRP1 \ + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \ + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \ + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + +#define MX27_CSPI2_PINGRP1 \ + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \ + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \ + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + +#define MX27_CSPI3_PINGRP1 \ + MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \ + MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \ + MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0 + +#define MX27_FB_PINGRP1 \ + MX27_PAD_CLS__CLS 0x0 \ + MX27_PAD_CONTRAST__CONTRAST 0x0 \ + MX27_PAD_LD0__LD0 0x0 \ + MX27_PAD_LD1__LD1 0x0 \ + MX27_PAD_LD2__LD2 0x0 \ + MX27_PAD_LD3__LD3 0x0 \ + MX27_PAD_LD4__LD4 0x0 \ + MX27_PAD_LD5__LD5 0x0 \ + MX27_PAD_LD6__LD6 0x0 \ + MX27_PAD_LD7__LD7 0x0 \ + MX27_PAD_LD8__LD8 0x0 \ + MX27_PAD_LD9__LD9 0x0 \ + MX27_PAD_LD10__LD10 0x0 \ + MX27_PAD_LD11__LD11 0x0 \ + MX27_PAD_LD12__LD12 0x0 \ + MX27_PAD_LD13__LD13 0x0 \ + MX27_PAD_LD14__LD14 0x0 \ + MX27_PAD_LD15__LD15 0x0 \ + MX27_PAD_LD16__LD16 0x0 \ + MX27_PAD_LD17__LD17 0x0 \ + MX27_PAD_LSCLK__LSCLK 0x0 \ + MX27_PAD_OE_ACD__OE_ACD 0x0 \ + MX27_PAD_PS__PS 0x0 \ + MX27_PAD_REV__REV 0x0 \ + MX27_PAD_SPL_SPR__SPL_SPR 0x0 \ + MX27_PAD_HSYNC__HSYNC 0x0 \ + MX27_PAD_VSYNC__VSYNC 0x0 + #define MX27_FEC1_PINGRP1 \ MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \ MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \ @@ -44,6 +88,30 @@ #define MX27_OWIRE1_PINGRP1 \ MX27_PAD_RTCK__OWIRE 0x0 +#define MX27_SDHC1_PINGRP1 \ + MX27_PAD_SD1_CLK__SD1_CLK \ + MX27_PAD_SD1_CMD__SD1_CMD \ + MX27_PAD_SD1_D0__SD1_D0 \ + MX27_PAD_SD1_D1__SD1_D1 \ + MX27_PAD_SD1_D2__SD1_D2 \ + MX27_PAD_SD1_D3__SD1_D3 + +#define MX27_SDHC2_PINGRP1 \ + MX27_PAD_SD2_CLK__SD2_CLK \ + MX27_PAD_SD2_CMD__SD2_CMD \ + MX27_PAD_SD2_D0__SD2_D0 \ + MX27_PAD_SD2_D1__SD2_D1 \ + MX27_PAD_SD2_D2__SD2_D2 \ + MX27_PAD_SD2_D3__SD2_D3 + +#define MX27_SDHC3_PINGRP1 \ + MX27_PAD_SD3_CLK__SD3_CLK \ + MX27_PAD_SD3_CMD__SD3_CMD \ + MX27_PAD_SD3_D0__SD3_D0 \ + MX27_PAD_SD3_D1__SD3_D1 \ + MX27_PAD_SD3_D2__SD3_D2 \ + MX27_PAD_SD3_D3__SD3_D3 + #define MX27_UART1_PINGRP1 \ MX27_PAD_UART1_TXD__UART1_TXD 0x0 \ MX27_PAD_UART1_RXD__UART1_RXD 0x0