From patchwork Wed Dec 4 22:52:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3285661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DA66DC0D4A for ; Wed, 4 Dec 2013 22:56:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EEF9C203B4 for ; Wed, 4 Dec 2013 22:56:03 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2D1F201BA for ; Wed, 4 Dec 2013 22:56:02 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoLLy-0007oT-MY; Wed, 04 Dec 2013 22:55:34 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoLLs-0003yr-Me; Wed, 04 Dec 2013 22:55:28 +0000 Received: from tx2ehsobe004.messaging.microsoft.com ([65.55.88.14] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VoLLc-0003wV-UP for linux-arm-kernel@lists.infradead.org; Wed, 04 Dec 2013 22:55:14 +0000 Received: from mail193-tx2-R.bigfish.com (10.9.14.239) by TX2EHSOBE009.bigfish.com (10.9.40.29) with Microsoft SMTP Server id 14.1.225.22; Wed, 4 Dec 2013 22:54:54 +0000 Received: from mail193-tx2 (localhost [127.0.0.1]) by mail193-tx2-R.bigfish.com (Postfix) with ESMTP id 02ECE601BE; Wed, 4 Dec 2013 22:54:54 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail193-tx2: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail193-tx2 (localhost.localdomain [127.0.0.1]) by mail193-tx2 (MessageSwitch) id 1386197692691471_31741; Wed, 4 Dec 2013 22:54:52 +0000 (UTC) Received: from TX2EHSMHS009.bigfish.com (unknown [10.9.14.254]) by mail193-tx2.bigfish.com (Postfix) with ESMTP id 9CCF2201E9; Wed, 4 Dec 2013 22:54:52 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by TX2EHSMHS009.bigfish.com (10.9.99.109) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 4 Dec 2013 22:54:51 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Wed, 4 Dec 2013 14:43:00 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rB4Msjnd002799; Wed, 4 Dec 2013 14:54:50 -0800 (PST) From: To: , , , , , , , , , Subject: [PATCHv3 3/4] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific funcationality Date: Wed, 4 Dec 2013 16:52:55 -0600 Message-ID: <1386197576-3825-4-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386197576-3825-1-git-send-email-dinguyen@altera.com> References: <1386197576-3825-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131204_175513_152463_9A4EE31D X-CRM114-Status: GOOD ( 13.37 ) X-Spam-Score: -4.2 (----) Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The SDR timing registers for the SD/MMC IP block for SOCFPGA is located in the system manager. This system manager IP block is located outside of the SD IP block itself. We can use the normal clock API to set the SDR settings. Also, there is no need for "altr,dw-mshc-ciu-div" as the driver can get the value of the CIU clock from the common clock API. Signed-off-by: Dinh Nguyen --- v3: none v2: none --- drivers/mmc/host/dw_mmc-socfpga.c | 78 +++++-------------------------------- 1 file changed, 10 insertions(+), 68 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c index 3e8e53a..d790cc0 100644 --- a/drivers/mmc/host/dw_mmc-socfpga.c +++ b/drivers/mmc/host/dw_mmc-socfpga.c @@ -13,95 +13,37 @@ * Taken from dw_mmc-exynos.c */ #include -#include #include #include #include #include #include -#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" -#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) - -/* SOCFPGA implementation specific driver private data */ -struct dw_mci_socfpga_priv_data { - u8 ciu_div; /* card interface unit divisor */ - u32 hs_timing; /* bitmask for CIU clock phase shift */ - struct regmap *sysreg; /* regmap for system manager register */ -}; - -static int dw_mci_socfpga_priv_init(struct dw_mci *host) -{ - return 0; -} - static int dw_mci_socfpga_setup_clock(struct dw_mci *host) { - struct dw_mci_socfpga_priv_data *priv = host->priv; - - clk_disable_unprepare(host->ciu_clk); - regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET, - priv->hs_timing); - clk_prepare_enable(host->ciu_clk); - - host->bus_hz /= (priv->ciu_div + 1); + struct clk *sysmgr_clk = devm_clk_get(host->dev, "sysmgr-sdr-mmc"); + + if (IS_ERR(sysmgr_clk)) + dev_err(host->dev, "sysmgr-sdr-mmc not available\n"); + else { + clk_disable_unprepare(host->ciu_clk); + clk_prepare_enable(sysmgr_clk); + clk_prepare_enable(host->ciu_clk); + } return 0; } static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr) { - struct dw_mci_socfpga_priv_data *priv = host->priv; - - if (priv->hs_timing & DRV_CLK_PHASE_SHIFT_SEL_MASK) - *cmdr |= SDMMC_CMD_USE_HOLD_REG; -} - -static int dw_mci_socfpga_parse_dt(struct dw_mci *host) -{ - struct dw_mci_socfpga_priv_data *priv; - struct device_node *np = host->dev->of_node; - u32 timing[2]; - u32 div = 0; - int ret; - - priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(host->dev, "mem alloc failed for private data\n"); - return -ENOMEM; - } - - priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(priv->sysreg)) { - dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); - return PTR_ERR(priv->sysreg); - } - - ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); - if (ret) - dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); - priv->ciu_div = div; - - ret = of_property_read_u32_array(np, - "altr,dw-mshc-sdr-timing", timing, 2); - if (ret) - return ret; - - priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); - host->priv = priv; - return 0; + *cmdr |= SDMMC_CMD_USE_HOLD_REG; } static const struct dw_mci_drv_data socfpga_drv_data = { - .init = dw_mci_socfpga_priv_init, .setup_clock = dw_mci_socfpga_setup_clock, .prepare_command = dw_mci_socfpga_prepare_command, - .parse_dt = dw_mci_socfpga_parse_dt, }; static const struct of_device_id dw_mci_socfpga_match[] = {