From patchwork Wed Dec 11 07:54:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 3322861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2E7939F37A for ; Wed, 11 Dec 2013 08:13:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C049C20720 for ; Wed, 11 Dec 2013 08:13:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0AABF20715 for ; Wed, 11 Dec 2013 08:13:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqefp-0004BY-Hu; Wed, 11 Dec 2013 07:57:38 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqef6-0002QB-Fg; Wed, 11 Dec 2013 07:56:52 +0000 Received: from mail-pb0-f47.google.com ([209.85.160.47]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VqeeA-0002Il-Ft for linux-arm-kernel@lists.infradead.org; Wed, 11 Dec 2013 07:55:59 +0000 Received: by mail-pb0-f47.google.com with SMTP id um1so9406267pbc.34 for ; Tue, 10 Dec 2013 23:55:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tTyVb0gU55HVE1reQRNTlBduirwLBt+fbqPVPn/9v4k=; b=LteTOgPqaQld1naYPDCtCPvceEf+gRIqwujcrYfq8a6mtpts+6CI157CtrSk1yaTy0 0xGYsApFXsTtSyZ7dXaYUBDb/6/nMAEtxz3vyDGfHaje11XHcqSU6eWTzhE17MW3RhdZ NA8Scradbzg04nzFYXpK56xE2vPZGa1o9SW/1A+O+7H9KwQzZ6NtthiySDA5AAlMXsK7 BCwsFXft8jciLjmYSINS8LItlRT/pJ6L/mIPBo1r5KfWBe9h384qVeQQ0p4FyXuz6NpD gMpBGFqe7bNtv6XjHZurW9ZqzMhEvBWl7b1O+mYxFCxlXJg5AtTTfcAOdjabU7+ldyOD XWCQ== X-Gm-Message-State: ALoCoQlhiV4n54I3f2Xxw3uZxyDi4HtTWh8W8AFXMqnYNLvgqyaaaXbv7gJ0yb997TBq6HPpxFLT X-Received: by 10.69.11.228 with SMTP id el4mr184208pbd.8.1386748538279; Tue, 10 Dec 2013 23:55:38 -0800 (PST) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id qz9sm30647313pbc.3.2013.12.10.23.55.34 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 10 Dec 2013 23:55:37 -0800 (PST) From: Haojian Zhuang To: olof@lixom.net, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, patches@linaro.org, khilman@linaro.org Subject: [PATCH v12 07/08] ARM: dts: enable clock binding on Hi3620 Date: Wed, 11 Dec 2013 15:54:56 +0800 Message-Id: <1386748497-11290-8-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1386748497-11290-1-git-send-email-haojian.zhuang@gmail.com> References: <1386748497-11290-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131211_025554_751513_BC636E4A X-CRM114-Status: UNSURE ( 9.61 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable clock binding for Hi3620 common clock driver. Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/hi3620.dtsi | 79 ++++++++++++++++++++++++------------------- arch/arm/boot/dts/hi4511.dts | 3 +- 2 files changed, 46 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index e311937..ab1116d 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -11,7 +11,8 @@ * publishhed by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include / { aliases { @@ -63,6 +64,7 @@ }; amba { + #address-cells = <1>; #size-cells = <1>; compatible = "arm,amba-bus"; @@ -88,13 +90,20 @@ sysctrl: system-controller@802000 { compatible = "hisilicon,sysctrl"; - reg = <0x802000 0x1000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x802000 0x1000>; + reg = <0x802000 0x1000>; smp-offset = <0x31c>; resume-offset = <0x308>; reboot-offset = <0x4>; + + clock: clock@0 { + compatible = "hisilicon,hi3620-clock"; + reg = <0 0x10000>; + #clock-cells = <1>; + }; }; dual_timer0: dual_timer@800000 { @@ -102,7 +111,7 @@ reg = <0x800000 0x1000>; /* timer00 & timer01 */ interrupts = <0 0 4>, <0 1 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -112,7 +121,7 @@ reg = <0x801000 0x1000>; /* timer10 & timer11 */ interrupts = <0 2 4>, <0 3 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -122,7 +131,7 @@ reg = <0xa01000 0x1000>; /* timer20 & timer21 */ interrupts = <0 4 4>, <0 5 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -132,7 +141,7 @@ reg = <0xa02000 0x1000>; /* timer30 & timer31 */ interrupts = <0 6 4>, <0 7 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -142,7 +151,7 @@ reg = <0xa03000 0x1000>; /* timer40 & timer41 */ interrupts = <0 96 4>, <0 97 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -157,7 +166,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xb00000 0x1000>; interrupts = <0 20 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_UARTCLK0>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -166,7 +175,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xb01000 0x1000>; interrupts = <0 21 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_UARTCLK1>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -175,7 +184,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xb02000 0x1000>; interrupts = <0 22 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_UARTCLK2>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -184,7 +193,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xb03000 0x1000>; interrupts = <0 23 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_UARTCLK3>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -193,7 +202,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 24 4>; - clocks = <&pclk>; + clocks = <&clock HI3620_UARTCLK4>; clock-names = "apb_pclk"; status = "disabled"; }; @@ -208,7 +217,7 @@ &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK0>; clock-names = "apb_pclk"; }; @@ -223,7 +232,7 @@ &pmx0 6 5 1 &pmx0 7 6 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK1>; clock-names = "apb_pclk"; }; @@ -238,7 +247,7 @@ &pmx0 6 3 1 &pmx0 7 3 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK2>; clock-names = "apb_pclk"; }; @@ -253,7 +262,7 @@ &pmx0 6 11 1 &pmx0 7 11 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK3>; clock-names = "apb_pclk"; }; @@ -268,7 +277,7 @@ &pmx0 6 13 1 &pmx0 7 13 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK4>; clock-names = "apb_pclk"; }; @@ -283,7 +292,7 @@ &pmx0 6 16 1 &pmx0 7 16 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK5>; clock-names = "apb_pclk"; }; @@ -298,7 +307,7 @@ &pmx0 6 18 1 &pmx0 7 19 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK6>; clock-names = "apb_pclk"; }; @@ -313,7 +322,7 @@ &pmx0 6 25 1 &pmx0 7 26 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK7>; clock-names = "apb_pclk"; }; @@ -328,7 +337,7 @@ &pmx0 6 33 1 &pmx0 7 34 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK8>; clock-names = "apb_pclk"; }; @@ -343,7 +352,7 @@ &pmx0 6 41 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK9>; clock-names = "apb_pclk"; }; @@ -357,7 +366,7 @@ &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK10>; clock-names = "apb_pclk"; }; @@ -372,7 +381,7 @@ &pmx0 6 49 1 &pmx0 7 49 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK11>; clock-names = "apb_pclk"; }; @@ -387,7 +396,7 @@ &pmx0 6 51 1 &pmx0 7 52 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK12>; clock-names = "apb_pclk"; }; @@ -402,7 +411,7 @@ &pmx0 6 55 1 &pmx0 7 56 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK13>; clock-names = "apb_pclk"; }; @@ -417,7 +426,7 @@ &pmx0 6 60 1 &pmx0 7 61 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK14>; clock-names = "apb_pclk"; }; @@ -432,7 +441,7 @@ &pmx0 6 64 1 &pmx0 7 65 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK15>; clock-names = "apb_pclk"; }; @@ -447,7 +456,7 @@ &pmx0 6 72 1 &pmx0 7 73 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK16>; clock-names = "apb_pclk"; }; @@ -462,7 +471,7 @@ &pmx0 6 80 1 &pmx0 7 81 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK17>; clock-names = "apb_pclk"; }; @@ -477,7 +486,7 @@ &pmx0 6 86 1 &pmx0 7 87 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK18>; clock-names = "apb_pclk"; }; @@ -491,7 +500,7 @@ &pmx0 3 88 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK19>; clock-names = "apb_pclk"; }; @@ -505,7 +514,7 @@ &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK20>; clock-names = "apb_pclk"; }; @@ -518,7 +527,7 @@ gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pclk>; + clocks = <&clock HI3620_GPIOCLK21>; clock-names = "apb_pclk"; }; diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts index 96e69ab..fe62392 100644 --- a/arch/arm/boot/dts/hi4511.dts +++ b/arch/arm/boot/dts/hi4511.dts @@ -8,7 +8,8 @@ */ /dts-v1/; -/include/ "hi3620.dtsi" + +#include "hi3620.dtsi" / { model = "Hisilicon Hi4511 Development Board";