From patchwork Wed Dec 11 08:13:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 3322871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9DBD49F37A for ; Wed, 11 Dec 2013 08:14:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 768AC20720 for ; Wed, 11 Dec 2013 08:14:10 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D757620715 for ; Wed, 11 Dec 2013 08:14:08 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevl-0006em-QP; Wed, 11 Dec 2013 08:14:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevj-0002hN-5p; Wed, 11 Dec 2013 08:14:03 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevg-0002gy-EC for linux-arm-kernel@lists.infradead.org; Wed, 11 Dec 2013 08:14:01 +0000 Received: by mail-pb0-f49.google.com with SMTP id jt11so9357142pbb.8 for ; Wed, 11 Dec 2013 00:13:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=JFlKc/ym7U+ylZZNtsQpQKVxS8EartgXzBud/Ev/lEs=; b=i7F6j5C9JY1FX0hMQG0OKGXDDNqEzvnVdPChUUh0oJFf19MRJq4ZgeQ31ZCTqeKoca JsAh6FKx0iwvHsmAbhf1WcndR5+3b+lIllwjoy3ciFuNeYJpP4tXWyOooMu8ip0+LALl HvERAozi9nSyYTTy9506iEpnqZe5gYQFuag2KYhzFtQIR53Ve/tvq+Os6dWTHNwktMl8 p5HFVb99EWebWRpwRbtLB8hBdKwxEVl+WBvRxjgP1dsCZUrtP/21O4RTBM3GlsqsoNqU K3/7qQa28mK9tVpkqOIZe1fI2Ua75OZKCV9w3ynd2u1VBSadz4vpeoSrjVz8rTkFykCx Pj+A== X-Gm-Message-State: ALoCoQn61FFIc7AMIymDOwsta4Leu3NPAwNMsgNadDfin7vAK4WqG1lEMTocbzIRiigz0mQZ76IA X-Received: by 10.66.178.143 with SMTP id cy15mr65809pac.105.1386749618993; Wed, 11 Dec 2013 00:13:38 -0800 (PST) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id ha10sm30746448pbd.17.2013.12.11.00.13.36 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Dec 2013 00:13:37 -0800 (PST) From: Haojian Zhuang To: mturquette@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/02] clk: hi3620: fix wrong flags on divider Date: Wed, 11 Dec 2013 16:13:31 +0800 Message-Id: <1386749612-12437-1-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.3.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131211_031400_572163_E0C6FAF5 X-CRM114-Status: UNSURE ( 9.91 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang --- drivers/clk/hisilicon/clk-hi3620.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index b66b074..f0e779f 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -60,8 +60,8 @@ static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", }; static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", }; static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", }; static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", }; -static const char *sd_mux_p[] __initdata = { "armpll3", "armpll2", }; -static const char *mmc1_mux_p[] __initdata = { "armpll3", "armpll2", }; +static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", }; static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", }; static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", }; static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", }; @@ -74,8 +74,8 @@ static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", }; static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4", "armpll3", "armpll5", }; static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", }; -static const char *mmc2_mux_p[] __initdata = { "armpll3", "armpll2", }; -static const char *mmc3_mux_p[] __initdata = { "armpll3", "armpll2", }; +static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", }; +static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", }; /* fixed rate clocks */ @@ -137,13 +137,13 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initdata = { }; static struct hisi_divider_clock hi3620_div_clks[] __initdata = { - { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_MUX_HIWORD_MASK, NULL, }, - { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_MUX_HIWORD_MASK, NULL, }, + { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, + { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, }; static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = {