From patchwork Wed Dec 11 08:13:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 3322881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7B7D29F37A for ; Wed, 11 Dec 2013 08:14:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0E09820720 for ; Wed, 11 Dec 2013 08:14:47 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4903B20715 for ; Wed, 11 Dec 2013 08:14:45 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevx-0006kX-Ug; Wed, 11 Dec 2013 08:14:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevs-0002i6-B1; Wed, 11 Dec 2013 08:14:12 +0000 Received: from mail-pb0-f46.google.com ([209.85.160.46]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqevj-0002gz-17 for linux-arm-kernel@lists.infradead.org; Wed, 11 Dec 2013 08:14:05 +0000 Received: by mail-pb0-f46.google.com with SMTP id md12so9498839pbc.33 for ; Wed, 11 Dec 2013 00:13:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LDhEYCAhB2Zb+c0V0j2nZUCa3uwGfZAL1tAxMVLnaxo=; b=HCyt/6MdRepGWn43bWGPs6D0/8FMhtUVd4n5U2MX3SvihGkHu24yh2rc0Lc87v7sZs U4kN+oLgLEb/xRoLBi7wp28dI8zRkAwFWAOGVZWX7YLAQmHADJD2EQ1/Lfi6sBgoa7sh Ch3ZG5DUw3K49cRdzQ2dvvnk9iEhVmKfvFrkRM7QJSTm6sTgafyc86cMooxW5cZBJYZ3 beDNfIt/W8xN96ZpZpg1bjoXh91GN1dDxZNombsBX0eOn7GwtShQxtFyOpHhlLs0D+UT yoBOdMw3dI33myMtS6PfYAdRYZYnMae2f7Gh6dEuq6O+ypIPqdVTFYa76RMivFxiPBEI 3ExA== X-Gm-Message-State: ALoCoQkd8IDNTqljUmddeJCz73QzA0uIB71plJzAEroxsu5fJrdFeiSQtB5RX7Yq2tRcI9T48jHc X-Received: by 10.68.103.163 with SMTP id fx3mr114895pbb.59.1386749621768; Wed, 11 Dec 2013 00:13:41 -0800 (PST) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id ha10sm30746448pbd.17.2013.12.11.00.13.39 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Dec 2013 00:13:40 -0800 (PST) From: Haojian Zhuang To: mturquette@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/02] clk: hi3620: add gate clock flag Date: Wed, 11 Dec 2013 16:13:32 +0800 Message-Id: <1386749612-12437-2-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1386749612-12437-1-git-send-email-haojian.zhuang@gmail.com> References: <1386749612-12437-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131211_031403_285233_6F6BA26B X-CRM114-Status: UNSURE ( 9.71 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang --- drivers/clk/hisilicon/clk-hi3620.c | 118 ++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index f0e779f..f24ad6a 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -147,65 +147,65 @@ static struct hisi_divider_clock hi3620_div_clks[] __initdata = { }; static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = { - { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", 0, 0x20, 0, 0, }, - { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", 0, 0x20, 1, 0, }, - { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", 0, 0x20, 2, 0, }, - { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", 0, 0x20, 3, 0, }, - { HI3620_RTCCLK, "rtcclk", "pclk", 0, 0x20, 5, 0, }, - { HI3620_KPC_CLK, "kpc_clk", "pclk", 0, 0x20, 6, 0, }, - { HI3620_GPIOCLK0, "gpioclk0", "pclk", 0, 0x20, 8, 0, }, - { HI3620_GPIOCLK1, "gpioclk1", "pclk", 0, 0x20, 9, 0, }, - { HI3620_GPIOCLK2, "gpioclk2", "pclk", 0, 0x20, 10, 0, }, - { HI3620_GPIOCLK3, "gpioclk3", "pclk", 0, 0x20, 11, 0, }, - { HI3620_GPIOCLK4, "gpioclk4", "pclk", 0, 0x20, 12, 0, }, - { HI3620_GPIOCLK5, "gpioclk5", "pclk", 0, 0x20, 13, 0, }, - { HI3620_GPIOCLK6, "gpioclk6", "pclk", 0, 0x20, 14, 0, }, - { HI3620_GPIOCLK7, "gpioclk7", "pclk", 0, 0x20, 15, 0, }, - { HI3620_GPIOCLK8, "gpioclk8", "pclk", 0, 0x20, 16, 0, }, - { HI3620_GPIOCLK9, "gpioclk9", "pclk", 0, 0x20, 17, 0, }, - { HI3620_GPIOCLK10, "gpioclk10", "pclk", 0, 0x20, 18, 0, }, - { HI3620_GPIOCLK11, "gpioclk11", "pclk", 0, 0x20, 19, 0, }, - { HI3620_GPIOCLK12, "gpioclk12", "pclk", 0, 0x20, 20, 0, }, - { HI3620_GPIOCLK13, "gpioclk13", "pclk", 0, 0x20, 21, 0, }, - { HI3620_GPIOCLK14, "gpioclk14", "pclk", 0, 0x20, 22, 0, }, - { HI3620_GPIOCLK15, "gpioclk15", "pclk", 0, 0x20, 23, 0, }, - { HI3620_GPIOCLK16, "gpioclk16", "pclk", 0, 0x20, 24, 0, }, - { HI3620_GPIOCLK17, "gpioclk17", "pclk", 0, 0x20, 25, 0, }, - { HI3620_GPIOCLK18, "gpioclk18", "pclk", 0, 0x20, 26, 0, }, - { HI3620_GPIOCLK19, "gpioclk19", "pclk", 0, 0x20, 27, 0, }, - { HI3620_GPIOCLK20, "gpioclk20", "pclk", 0, 0x20, 28, 0, }, - { HI3620_GPIOCLK21, "gpioclk21", "pclk", 0, 0x20, 29, 0, }, - { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", 0, 0x30, 15, 0, }, - { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", 0, 0x30, 16, 0, }, - { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", 0, 0x30, 17, 0, }, - { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", 0, 0x30, 24, 0, }, - { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", 0, 0x30, 28, 0, }, - { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", 0, 0x40, 3, 0, }, - { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", 0, 0x40, 4, 0, }, - { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", 0, 0x40, 5, 0, }, - { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", 0, 0x40, 7, 0, }, - { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", 0, 0x40, 8, 0, }, - { HI3620_UARTCLK0, "uartclk0", "uart0_mux", 0, 0x40, 16, 0, }, - { HI3620_UARTCLK1, "uartclk1", "uart1_mux", 0, 0x40, 17, 0, }, - { HI3620_UARTCLK2, "uartclk2", "uart2_mux", 0, 0x40, 18, 0, }, - { HI3620_UARTCLK3, "uartclk3", "uart3_mux", 0, 0x40, 19, 0, }, - { HI3620_UARTCLK4, "uartclk4", "uart4_mux", 0, 0x40, 20, 0, }, - { HI3620_SPICLK0, "spiclk0", "spi0_mux", 0, 0x40, 21, 0, }, - { HI3620_SPICLK1, "spiclk1", "spi1_mux", 0, 0x40, 22, 0, }, - { HI3620_SPICLK2, "spiclk2", "spi2_mux", 0, 0x40, 23, 0, }, - { HI3620_I2CCLK0, "i2cclk0", "pclk", 0, 0x40, 24, 0, }, - { HI3620_I2CCLK1, "i2cclk1", "pclk", 0, 0x40, 25, 0, }, - { HI3620_SCI_CLK, "sci_clk", "osc26m", 0, 0x40, 26, 0, }, - { HI3620_I2CCLK2, "i2cclk2", "pclk", 0, 0x40, 28, 0, }, - { HI3620_I2CCLK3, "i2cclk3", "pclk", 0, 0x40, 29, 0, }, - { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", 0, 0x50, 9, 0, }, - { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", 0, 0x50, 10, 0, }, - { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", 0, 0x50, 17, 0, }, - { HI3620_SD_CLK, "sd_clk", "sd_div", 0, 0x50, 20, 0, }, - { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", 0, 0x50, 21, 0, }, - { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", 0, 0x50, 22, 0, }, - { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", 0, 0x50, 23, 0, }, - { HI3620_MCU_CLK, "mcu_clk", "acp_clk", 0, 0x50, 24, 0, }, + { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, }, + { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, }, + { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, }, + { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, }, + { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, }, + { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, }, + { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, }, + { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, }, + { HI3620_GPIOCLK2, "gpioclk2", "pclk", CLK_SET_RATE_PARENT, 0x20, 10, 0, }, + { HI3620_GPIOCLK3, "gpioclk3", "pclk", CLK_SET_RATE_PARENT, 0x20, 11, 0, }, + { HI3620_GPIOCLK4, "gpioclk4", "pclk", CLK_SET_RATE_PARENT, 0x20, 12, 0, }, + { HI3620_GPIOCLK5, "gpioclk5", "pclk", CLK_SET_RATE_PARENT, 0x20, 13, 0, }, + { HI3620_GPIOCLK6, "gpioclk6", "pclk", CLK_SET_RATE_PARENT, 0x20, 14, 0, }, + { HI3620_GPIOCLK7, "gpioclk7", "pclk", CLK_SET_RATE_PARENT, 0x20, 15, 0, }, + { HI3620_GPIOCLK8, "gpioclk8", "pclk", CLK_SET_RATE_PARENT, 0x20, 16, 0, }, + { HI3620_GPIOCLK9, "gpioclk9", "pclk", CLK_SET_RATE_PARENT, 0x20, 17, 0, }, + { HI3620_GPIOCLK10, "gpioclk10", "pclk", CLK_SET_RATE_PARENT, 0x20, 18, 0, }, + { HI3620_GPIOCLK11, "gpioclk11", "pclk", CLK_SET_RATE_PARENT, 0x20, 19, 0, }, + { HI3620_GPIOCLK12, "gpioclk12", "pclk", CLK_SET_RATE_PARENT, 0x20, 20, 0, }, + { HI3620_GPIOCLK13, "gpioclk13", "pclk", CLK_SET_RATE_PARENT, 0x20, 21, 0, }, + { HI3620_GPIOCLK14, "gpioclk14", "pclk", CLK_SET_RATE_PARENT, 0x20, 22, 0, }, + { HI3620_GPIOCLK15, "gpioclk15", "pclk", CLK_SET_RATE_PARENT, 0x20, 23, 0, }, + { HI3620_GPIOCLK16, "gpioclk16", "pclk", CLK_SET_RATE_PARENT, 0x20, 24, 0, }, + { HI3620_GPIOCLK17, "gpioclk17", "pclk", CLK_SET_RATE_PARENT, 0x20, 25, 0, }, + { HI3620_GPIOCLK18, "gpioclk18", "pclk", CLK_SET_RATE_PARENT, 0x20, 26, 0, }, + { HI3620_GPIOCLK19, "gpioclk19", "pclk", CLK_SET_RATE_PARENT, 0x20, 27, 0, }, + { HI3620_GPIOCLK20, "gpioclk20", "pclk", CLK_SET_RATE_PARENT, 0x20, 28, 0, }, + { HI3620_GPIOCLK21, "gpioclk21", "pclk", CLK_SET_RATE_PARENT, 0x20, 29, 0, }, + { HI3620_DPHY0_CLK, "dphy0_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 15, 0, }, + { HI3620_DPHY1_CLK, "dphy1_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 16, 0, }, + { HI3620_DPHY2_CLK, "dphy2_clk", "osc26m", CLK_SET_RATE_PARENT, 0x30, 17, 0, }, + { HI3620_USBPHY_CLK, "usbphy_clk", "rclk_pico", CLK_SET_RATE_PARENT, 0x30, 24, 0, }, + { HI3620_ACP_CLK, "acp_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x30, 28, 0, }, + { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, }, + { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, }, + { HI3620_TIMERCLK89, "timerclk89", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 5, 0, }, + { HI3620_PWMCLK0, "pwmclk0", "pwm0_mux", CLK_SET_RATE_PARENT, 0x40, 7, 0, }, + { HI3620_PWMCLK1, "pwmclk1", "pwm1_mux", CLK_SET_RATE_PARENT, 0x40, 8, 0, }, + { HI3620_UARTCLK0, "uartclk0", "uart0_mux", CLK_SET_RATE_PARENT, 0x40, 16, 0, }, + { HI3620_UARTCLK1, "uartclk1", "uart1_mux", CLK_SET_RATE_PARENT, 0x40, 17, 0, }, + { HI3620_UARTCLK2, "uartclk2", "uart2_mux", CLK_SET_RATE_PARENT, 0x40, 18, 0, }, + { HI3620_UARTCLK3, "uartclk3", "uart3_mux", CLK_SET_RATE_PARENT, 0x40, 19, 0, }, + { HI3620_UARTCLK4, "uartclk4", "uart4_mux", CLK_SET_RATE_PARENT, 0x40, 20, 0, }, + { HI3620_SPICLK0, "spiclk0", "spi0_mux", CLK_SET_RATE_PARENT, 0x40, 21, 0, }, + { HI3620_SPICLK1, "spiclk1", "spi1_mux", CLK_SET_RATE_PARENT, 0x40, 22, 0, }, + { HI3620_SPICLK2, "spiclk2", "spi2_mux", CLK_SET_RATE_PARENT, 0x40, 23, 0, }, + { HI3620_I2CCLK0, "i2cclk0", "pclk", CLK_SET_RATE_PARENT, 0x40, 24, 0, }, + { HI3620_I2CCLK1, "i2cclk1", "pclk", CLK_SET_RATE_PARENT, 0x40, 25, 0, }, + { HI3620_SCI_CLK, "sci_clk", "osc26m", CLK_SET_RATE_PARENT, 0x40, 26, 0, }, + { HI3620_I2CCLK2, "i2cclk2", "pclk", CLK_SET_RATE_PARENT, 0x40, 28, 0, }, + { HI3620_I2CCLK3, "i2cclk3", "pclk", CLK_SET_RATE_PARENT, 0x40, 29, 0, }, + { HI3620_DDRC_PER_CLK, "ddrc_per_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 9, 0, }, + { HI3620_DMAC_CLK, "dmac_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 10, 0, }, + { HI3620_USB2DVC_CLK, "usb2dvc_clk", "rclk_cfgaxi", CLK_SET_RATE_PARENT, 0x50, 17, 0, }, + { HI3620_SD_CLK, "sd_clk", "sd_div", CLK_SET_RATE_PARENT, 0x50, 20, 0, }, + { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, }, + { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, }, + { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, }, + { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, }, }; static void __init hi3620_clk_init(struct device_node *np)