From patchwork Wed Dec 11 09:25:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 3323141 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D744B9F37A for ; Wed, 11 Dec 2013 09:26:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 46E7120136 for ; Wed, 11 Dec 2013 09:26:01 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05030200EA for ; Wed, 11 Dec 2013 09:26:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqg3G-0001ir-T4; Wed, 11 Dec 2013 09:25:55 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqg3E-0004GF-Hy; Wed, 11 Dec 2013 09:25:52 +0000 Received: from 82-68-191-81.dsl.posilan.com ([82.68.191.81] helo=rainbowdash.ducie.codethink.co.uk) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vqg3B-0004FH-A0 for linux-arm-kernel@lists.infradead.org; Wed, 11 Dec 2013 09:25:50 +0000 Received: from ben by rainbowdash.ducie.codethink.co.uk with local (Exim 4.82) (envelope-from ) id 1Vqg2f-0006gF-Ox; Wed, 11 Dec 2013 09:25:17 +0000 From: Ben Dooks To: horms@verge.net.au, magnus.damm@gmail.com, linux-sh@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: rcar-gen2: Do not attempt to re-setup timer if running correctly Date: Wed, 11 Dec 2013 09:25:16 +0000 Message-Id: <1386753916-25648-1-git-send-email-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 1.8.5.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131211_042549_493722_CB7554B1 X-CRM114-Status: GOOD ( 12.76 ) X-Spam-Score: -0.3 (/) Cc: linux-kernel@lists.codethink.co.uk, Ben Dooks X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the system has been started in non-secure mode, then the ARM generic timer is not configurable during the kernel initialisation. Currently the only thing we can check for is if the timer has been correctly configured during the boot process. Signed-off-by: Ben Dooks Reviewed-by: Ian Molton Acked-by: Magnus Damm --- arch/arm/mach-shmobile/setup-rcar-gen2.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 5734c24..6b7b7f1 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -78,12 +78,20 @@ void __init rcar_gen2_timer_init(void) /* Remap "armgcnt address map" space */ base = ioremap(0xe6080000, PAGE_SIZE); - /* Update registers with correct frequency */ - iowrite32(freq, base + CNTFID0); - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + /* Update the timer if it is either not running, or is not at the + * right frequency. The timer is only configurable in secure mode + * so this avoids an abort if the loader started the timer and + * started the kernel in non-secure mode. */ + if ((ioread32(base + CNTCR) & 1) == 0 || + ioread32(base + CNTFID0) != freq) { + /* Update registers with correct frequency */ + iowrite32(freq, base + CNTFID0); + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); + + /* make sure arch timer is started by setting bit 0 of CNTCR */ + iowrite32(1, base + CNTCR); + } - /* make sure arch timer is started by setting bit 0 of CNTCR */ - iowrite32(1, base + CNTCR); iounmap(base); #endif /* CONFIG_ARM_ARCH_TIMER */