| Message ID | 1386833435-30498-3-git-send-email-lho@apm.com (mailing list archive) |
|---|---|
| State | New, archived |
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On Thursday 12 December 2013, Loc Ho wrote: > +- reg : First PHY memory resource is the SDS PHY access > + resource. > + Second PHY memory resoruce is the clock and reset > + resources. > + Third PHY memory resource is the SDS PHY access > + resource outside of the IP if it is type > + "apm,xgene-phy-ext". Why do the "clock and reset" resources not use a clock driver and a reset driver? I would expect these to get replaced with clocks : Reference to external clock input resets : Reference to reset controller input > +Optional properties: > +- status : Shall be "ok" if enabled or "disabled" if disabled. > + Default is "ok". > +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial > + bit lines from the automatic calibrated position. > + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > + Range from 0 to 0x7f in unit of one bit period. > + Default is 0xa. What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them? Why are there two sets? Will this have to change if you add PCIe support? I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others. > +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample > + data earlier than the nominal sampling point. 1 means > + sample data later than the nominal sampling point. > + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > + Default is 0x0. > + > +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) > + gain control. Two set of 3-tuple setting for Gen1, > + Gen2, and Gen3. Range is between 0 to 0x1f in unit > + of dB. Default is 0x3. > + > +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for > + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in > + unit of 13.3mV. Default is 0xf. Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts. > +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of > + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > + between 0 to 0xf in unit of 18.2mV. Default is 0x0. > +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of > + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. > +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of > + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. Same here. > +- apm,tx-speed : Tx operating speed. One set of 3-tuple for > + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is > + 0x7. I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property. Arnd
On 13-12-12 02:27 PM, Arnd Bergmann wrote: > On Thursday 12 December 2013, Loc Ho wrote: >> +- reg : First PHY memory resource is the SDS PHY access >> + resource. >> + Second PHY memory resoruce is the clock and reset >> + resources. >> + Third PHY memory resource is the SDS PHY access >> + resource outside of the IP if it is type >> + "apm,xgene-phy-ext". > > Why do the "clock and reset" resources not use a clock driver and a reset > driver? > > I would expect these to get replaced with > > clocks : Reference to external clock input > resets : Reference to reset controller input > >> +Optional properties: >> +- status : Shall be "ok" if enabled or "disabled" if disabled. >> + Default is "ok". >> +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial >> + bit lines from the automatic calibrated position. >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> + Range from 0 to 0x7f in unit of one bit period. >> + Default is 0xa. > > What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations > or all of them? > > Why are there two sets? > > Will this have to change if you add PCIe support? > > I would suggest using decimal notation here instead of hexadecimal since you > are dealing with numbers couting things. Same for the others. > >> +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample >> + data earlier than the nominal sampling point. 1 means >> + sample data later than the nominal sampling point. >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> + Default is 0x0. >> + >> +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) >> + gain control. Two set of 3-tuple setting for Gen1, >> + Gen2, and Gen3. Range is between 0 to 0x1f in unit >> + of dB. Default is 0x3. >> + >> +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for >> + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in >> + unit of 13.3mV. Default is 0xf. > > Units of 13.3mV don't seem to be useful as a generic measurement. I'd > recommend using milivolts or microvolts. > >> +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0xf in unit of 18.2mV. Default is 0x0. >> +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. >> +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. > > Same here. > >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is >> + 0x7. > > I'm completely confused by this description. Can you rephrase this? > It sounds like the only possible values are <1 3 7> for this property. Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3: G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 Gbps And the "7" corresponding to Gen3 is indicating backward compatibility with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility two generations. Thus you can buy a SAS 12 Gbps HBA today that will not support the original SATA 1.5 Gbps class of disks. The corresponding value would be 0xe (rather than 0xf) using the tx-speed convention above. My explanation is a bit long winded to put in a device-tree bindings file. "RTFM: SATA drafts." should suffice. BTW Compared to some device-tree binding explanations I have had to wade through, the above looks pretty good. Doug Gilbert
Hi, > On Thursday 12 December 2013, Loc Ho wrote: >> +- reg : First PHY memory resource is the SDS PHY access >> + resource. >> + Second PHY memory resoruce is the clock and reset >> + resources. >> + Third PHY memory resource is the SDS PHY access >> + resource outside of the IP if it is type >> + "apm,xgene-phy-ext". > > Why do the "clock and reset" resources not use a clock driver and a reset > driver? > > I would expect these to get replaced with > > clocks : Reference to external clock input > resets : Reference to reset controller input [Loc Ho] The clock register has bit for the SDS interface, each sata ports, CSR, AXI interface, and the PM (power management) interface. The clock and CSR for all these are enabled by the host controller driver. Unfortunately, during calibration the SATA ports clocks must not be enable. This sequence is required by the hardware itself. Unless I separate out the two, this requirement is handled by the PHY. If you believe this is needed, I can have two separate clocks but it is over kill. You can look at function xgene_phy_sata_setup_preclk and xgene_phy_sata_setup_postclk. > >> +Optional properties: >> +- status : Shall be "ok" if enabled or "disabled" if disabled. >> + Default is "ok". >> +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial >> + bit lines from the automatic calibrated position. >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> + Range from 0 to 0x7f in unit of one bit period. >> + Default is 0xa. > > What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations > or all of them? [Loc Ho] Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 is 3.0Gbps, and Gen3 is 6Gbps. > > Why are there two sets? [Loc Ho] Each controller has two SATA ports - one set for each port. > > Will this have to change if you add PCIe support? [Loc Ho] So far, we don't see a need to use override setting for PCIe > > I would suggest using decimal notation here instead of hexadecimal since you > are dealing with numbers couting things. Same for the others. [Loc Ho] Okay... for future version. > >> +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample >> + data earlier than the nominal sampling point. 1 means >> + sample data later than the nominal sampling point. >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> + Default is 0x0. >> + >> +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) >> + gain control. Two set of 3-tuple setting for Gen1, >> + Gen2, and Gen3. Range is between 0 to 0x1f in unit >> + of dB. Default is 0x3. >> + >> +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for >> + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in >> + unit of 13.3mV. Default is 0xf. > > Units of 13.3mV don't seem to be useful as a generic measurement. I'd > recommend using milivolts or microvolts. [Loc Ho] Each unit is 13.3mV. If I use millivolt, then someone can set fraction which will get round up or down. If you still strongly suggest this is required, then fine. > >> +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0xf in unit of 18.2mV. Default is 0x0. >> +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. >> +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. > > Same here. > >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is >> + 0x7. > > I'm completely confused by this description. Can you rephrase this? > It sounds like the only possible values are <1 3 7> for this property. [Loc Ho] Douglas already comment on this. If you believe this needs to be rephrased, then let me know. -Loc
On Thu, 2013-12-12 at 15:31 +0100, Douglas Gilbert wrote: > On 13-12-12 02:27 PM, Arnd Bergmann wrote: > > On Thursday 12 December 2013, Loc Ho wrote: > >> +- reg : First PHY memory resource is the SDS PHY access > >> + resource. > >> + Second PHY memory resoruce is the clock and reset > >> + resources. > >> + Third PHY memory resource is the SDS PHY access > >> + resource outside of the IP if it is type > >> + "apm,xgene-phy-ext". > > > > Why do the "clock and reset" resources not use a clock driver and a reset > > driver? > > > > I would expect these to get replaced with > > > > clocks : Reference to external clock input > > resets : Reference to reset controller input > > > >> +Optional properties: > >> +- status : Shall be "ok" if enabled or "disabled" if disabled. > >> + Default is "ok". > >> +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial > >> + bit lines from the automatic calibrated position. > >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > >> + Range from 0 to 0x7f in unit of one bit period. > >> + Default is 0xa. > > > > What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations > > or all of them? > > > > Why are there two sets? > > > > Will this have to change if you add PCIe support? > > > > I would suggest using decimal notation here instead of hexadecimal since you > > are dealing with numbers couting things. Same for the others. > > > >> +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample > >> + data earlier than the nominal sampling point. 1 means > >> + sample data later than the nominal sampling point. > >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > >> + Default is 0x0. > >> + > >> +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) > >> + gain control. Two set of 3-tuple setting for Gen1, > >> + Gen2, and Gen3. Range is between 0 to 0x1f in unit > >> + of dB. Default is 0x3. > >> + > >> +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for > >> + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in > >> + unit of 13.3mV. Default is 0xf. > > > > Units of 13.3mV don't seem to be useful as a generic measurement. I'd > > recommend using milivolts or microvolts. > > > >> +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0xf in unit of 18.2mV. Default is 0x0. > >> +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. > >> +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. > > > > Same here. > > > >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for > >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is > >> + 0x7. > > > > I'm completely confused by this description. Can you rephrase this? > > It sounds like the only possible values are <1 3 7> for this property. > > Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's > G1, G2 and G3: > > G1 Gen1 1.5 Gbps > G2 Gen2 3 Gbps > G3 Gen3 6 Gbps > G4 - 12 Gbps > G5 - 24 Gbps Electrically, SAS phys and SATA phys are identical. We already have a SAS phy abstraction in libsas ... when looking at a separable phy implementation, shouldn't we be doing something that works for both instead of just SATA? James
On Thursday 12 December 2013, Douglas Gilbert wrote: > > > >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for > >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is > >> + 0x7. > > > > I'm completely confused by this description. Can you rephrase this? > > It sounds like the only possible values are <1 3 7> for this property. > > Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's > G1, G2 and G3: > > G1 Gen1 1.5 Gbps > G2 Gen2 3 Gbps > G3 Gen3 6 Gbps > G4 - 12 Gbps > G5 - 24 Gbps > > And the "7" corresponding to Gen3 is indicating backward compatibility > with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility > two generations. Thus you can buy a SAS 12 Gbps HBA today that will > not support the original SATA 1.5 Gbps class of disks. The corresponding > value would be 0xe (rather than 0xf) using the tx-speed convention above. > > > My explanation is a bit long winded to put in a device-tree bindings > file. "RTFM: SATA drafts." should suffice. > > > BTW Compared to some device-tree binding explanations I have had > to wade through, the above looks pretty good. > Well, the problem is that this is not a SATA device but a PHY device that happens to support SATA among its protocols (at least PCIe as well, possibly more but I don't have the specs). The binding document has to cover all the possibilities or allow extensions for the other protocols to be implemented later. Having the driver support SATA only initially is fine, but we shouldn't plan for breaking compatibility with an established binding just a short time later. Arnd
On Thursday 12 December 2013, James Bottomley wrote: > > > I'm completely confused by this description. Can you rephrase this? > > > It sounds like the only possible values are <1 3 7> for this property. > > > > Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's > > G1, G2 and G3: > > > > G1 Gen1 1.5 Gbps > > G2 Gen2 3 Gbps > > G3 Gen3 6 Gbps > > G4 - 12 Gbps > > G5 - 24 Gbps > > Electrically, SAS phys and SATA phys are identical. We already have a > SAS phy abstraction in libsas ... when looking at a separable phy > implementation, shouldn't we be doing something that works for both > instead of just SATA? This PHY is also used for ethernet and for PCIe, even though the driver handles only the SATA case so far. Can the SAS abstraction deal with this? How do you describe a SAS PHY in DT? Arnd
On Thursday 12 December 2013, Loc Ho wrote: > Hi, > > > On Thursday 12 December 2013, Loc Ho wrote: > >> +- reg : First PHY memory resource is the SDS PHY access > >> + resource. > >> + Second PHY memory resoruce is the clock and reset > >> + resources. > >> + Third PHY memory resource is the SDS PHY access > >> + resource outside of the IP if it is type > >> + "apm,xgene-phy-ext". > > > > Why do the "clock and reset" resources not use a clock driver and a reset > > driver? > > > > I would expect these to get replaced with > > > > clocks : Reference to external clock input > > resets : Reference to reset controller input > [Loc Ho] > The clock register has bit for the SDS interface, each sata ports, > CSR, AXI interface, and the PM (power management) interface. The clock > and CSR for all these are enabled by the host controller driver. > Unfortunately, during calibration the SATA ports clocks must not be > enable. This sequence is required by the hardware itself. Unless I > separate out the two, this requirement is handled by the PHY. If you > believe this is needed, I can have two separate clocks but it is over > kill. You can look at function xgene_phy_sata_setup_preclk and > xgene_phy_sata_setup_postclk. I'm not looking at this from the driver side but rather from the way the hardware is built. My understanding is that you have clock and reset registers in a separate register file that also handles clocks and reset lines for other devices with the same layout. If this is true, you should definitely write a clock driver and a reset driver to support the respective register layouts, and use the clock and reset APIs in the kernel to call them, rather than poking the raw registers from an unrelated driver. > >> +Optional properties: > >> +- status : Shall be "ok" if enabled or "disabled" if disabled. > >> + Default is "ok". > >> +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial > >> + bit lines from the automatic calibrated position. > >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > >> + Range from 0 to 0x7f in unit of one bit period. > >> + Default is 0xa. > > > > What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations > > or all of them? > [Loc Ho] > Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 > is 3.0Gbps, and Gen3 is 6Gbps. > > > > > Why are there two sets? > [Loc Ho] > Each controller has two SATA ports - one set for each port. Ok. > > Will this have to change if you add PCIe support? > [Loc Ho] > So far, we don't see a need to use override setting for PCIe The problem is that with the encoding you have chosen, it becomes a lot harder to add that if it turns out to be needed later. > > I would suggest using decimal notation here instead of hexadecimal since you > > are dealing with numbers couting things. Same for the others. > [Loc Ho] > Okay... for future version. > > > > >> +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample > >> + data earlier than the nominal sampling point. 1 means > >> + sample data later than the nominal sampling point. > >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. > >> + Default is 0x0. > >> + > >> +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) > >> + gain control. Two set of 3-tuple setting for Gen1, > >> + Gen2, and Gen3. Range is between 0 to 0x1f in unit > >> + of dB. Default is 0x3. > >> + > >> +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for > >> + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in > >> + unit of 13.3mV. Default is 0xf. > > > > Units of 13.3mV don't seem to be useful as a generic measurement. I'd > > recommend using milivolts or microvolts. > [Loc Ho] > Each unit is 13.3mV. If I use millivolt, then someone can set fraction > which will get round up or down. If you still strongly suggest this is > required, then fine. The amplitude sounds like something that a lot of PHY drivers would need to set, and we really want everybody to use the same property definitions for describing the same things. > >> +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0xf in unit of 18.2mV. Default is 0x0. > >> +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. > >> +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of > >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is > >> + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. > > > > Same here. > > > >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for > >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is > >> + 0x7. > > > > I'm completely confused by this description. Can you rephrase this? > > It sounds like the only possible values are <1 3 7> for this property. > [Loc Ho] > Douglas already comment on this. If you believe this needs to be > rephrased, then let me know. I think it's still rather confusing to the casual reader. Let me try to rephrase what I understand and you can decide whether you want to use that text, or correct my mistakes. apm,sata-speed : Tx operating speed for SATA mode. A 3-tuple for each supported link speed on the host, with a bit mask of compatible device speeds, encoded as 0x0001 - SATA-I (1.5gbits/s) 0x0002 - SATA-II (3.0gbits/s) 0x0004 - SATA-6G (6.0gbits/s) Default is <0x1 0x3 0x7>. Arnd
Hi, On Thu, Dec 12, 2013 at 12:29 PM, Arnd Bergmann <arnd@arndb.de> wrote: > On Thursday 12 December 2013, Douglas Gilbert wrote: >> > >> >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for >> >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is >> >> + 0x7. >> > >> > I'm completely confused by this description. Can you rephrase this? >> > It sounds like the only possible values are <1 3 7> for this property. >> >> Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's >> G1, G2 and G3: >> >> G1 Gen1 1.5 Gbps >> G2 Gen2 3 Gbps >> G3 Gen3 6 Gbps >> G4 - 12 Gbps >> G5 - 24 Gbps >> >> And the "7" corresponding to Gen3 is indicating backward compatibility >> with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility >> two generations. Thus you can buy a SAS 12 Gbps HBA today that will >> not support the original SATA 1.5 Gbps class of disks. The corresponding >> value would be 0xe (rather than 0xf) using the tx-speed convention above. >> >> >> My explanation is a bit long winded to put in a device-tree bindings >> file. "RTFM: SATA drafts." should suffice. >> >> >> BTW Compared to some device-tree binding explanations I have had >> to wade through, the above looks pretty good. >> > > Well, the problem is that this is not a SATA device but a PHY device > that happens to support SATA among its protocols (at least PCIe > as well, possibly more but I don't have the specs). The binding > document has to cover all the possibilities or allow extensions > for the other protocols to be implemented later. Having the driver > support SATA only initially is fine, but we shouldn't plan for > breaking compatibility with an established binding just a short time > later. > [Loc Ho] I will document them as XXGbps and drop the term GenX. As of right now, we only have SATA and I will document on 1.5Gbps, 3.0Gbps, and 6Gbps. Also, keep in mind that these override are used for SATA. PCIe doesn't need these custom override setting per port at this time. A single value so far work just fine for PCIe, SGMII, and XFI. Any other comments... -Loc
HI, >> >> +- reg : First PHY memory resource is the SDS PHY access >> >> + resource. >> >> + Second PHY memory resoruce is the clock and reset >> >> + resources. >> >> + Third PHY memory resource is the SDS PHY access >> >> + resource outside of the IP if it is type >> >> + "apm,xgene-phy-ext". >> > >> > Why do the "clock and reset" resources not use a clock driver and a reset >> > driver? >> > >> > I would expect these to get replaced with >> > >> > clocks : Reference to external clock input >> > resets : Reference to reset controller input >> [Loc Ho] >> The clock register has bit for the SDS interface, each sata ports, >> CSR, AXI interface, and the PM (power management) interface. The clock >> and CSR for all these are enabled by the host controller driver. >> Unfortunately, during calibration the SATA ports clocks must not be >> enable. This sequence is required by the hardware itself. Unless I >> separate out the two, this requirement is handled by the PHY. If you >> believe this is needed, I can have two separate clocks but it is over >> kill. You can look at function xgene_phy_sata_setup_preclk and >> xgene_phy_sata_setup_postclk. > > > I'm not looking at this from the driver side but rather from the way the > hardware is built. My understanding is that you have clock and reset > registers in a separate register file that also handles clocks and reset > lines for other devices with the same layout. If this is true, you > should definitely write a clock driver and a reset driver to support > the respective register layouts, and use the clock and reset APIs > in the kernel to call them, rather than poking the raw registers from > an unrelated driver. The HW has one clock register and one CSR (configuration status register) for all SATA and PHY sub-HW block. Each bit corresponding to one sub-HW block. In a perfect HW, one would just enable the clock and take the CSR out of reset and then go on initialize the HW. But there is an requirement to have some sub-HW block remain in reset until it is completed. It sounds like to me that I will need to separate them out. I will separate the clock interface into two components - one for the host and one for the PHY. > >> >> +Optional properties: >> >> +- status : Shall be "ok" if enabled or "disabled" if disabled. >> >> + Default is "ok". >> >> +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial >> >> + bit lines from the automatic calibrated position. >> >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> >> + Range from 0 to 0x7f in unit of one bit period. >> >> + Default is 0xa. >> > >> > What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations >> > or all of them? >> [Loc Ho] >> Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 >> is 3.0Gbps, and Gen3 is 6Gbps. >> >> > >> > Why are there two sets? >> [Loc Ho] >> Each controller has two SATA ports - one set for each port. > > Ok. > >> > Will this have to change if you add PCIe support? >> [Loc Ho] >> So far, we don't see a need to use override setting for PCIe > > The problem is that with the encoding you have chosen, it becomes a lot harder > to add that if it turns out to be needed later. [Loc Ho] PCIe also has Gen1, Gen2, and Gen3. USB has 1.1, 2.0, and 3.0. XSGMII is only 1Gbps. XFI is only 10Gbps. Let me put this in the text. > >> > I would suggest using decimal notation here instead of hexadecimal since you >> > are dealing with numbers couting things. Same for the others. >> [Loc Ho] >> Okay... for future version. >> >> > >> >> +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample >> >> + data earlier than the nominal sampling point. 1 means >> >> + sample data later than the nominal sampling point. >> >> + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. >> >> + Default is 0x0. >> >> + >> >> +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) >> >> + gain control. Two set of 3-tuple setting for Gen1, >> >> + Gen2, and Gen3. Range is between 0 to 0x1f in unit >> >> + of dB. Default is 0x3. >> >> + >> >> +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for >> >> + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in >> >> + unit of 13.3mV. Default is 0xf. >> > >> > Units of 13.3mV don't seem to be useful as a generic measurement. I'd >> > recommend using milivolts or microvolts. >> [Loc Ho] >> Each unit is 13.3mV. If I use millivolt, then someone can set fraction >> which will get round up or down. If you still strongly suggest this is >> required, then fine. > > The amplitude sounds like something that a lot of PHY drivers would need to > set, and we really want everybody to use the same property definitions for > describing the same things. [Loc Ho] Okay... I understand and stay with millivolt and let the driver handle the conversion > >> >> +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of >> >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> >> + between 0 to 0xf in unit of 18.2mV. Default is 0x0. >> >> +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of >> >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> >> + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. >> >> +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of >> >> + 3-tuple setting for Gen1, Gen2, and Gen3. Range is >> >> + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. >> > >> > Same here. >> > >> >> +- apm,tx-speed : Tx operating speed. One set of 3-tuple for >> >> + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is >> >> + 0x7. >> > >> > I'm completely confused by this description. Can you rephrase this? >> > It sounds like the only possible values are <1 3 7> for this property. >> [Loc Ho] >> Douglas already comment on this. If you believe this needs to be >> rephrased, then let me know. > > I think it's still rather confusing to the casual reader. Let me try to rephrase > what I understand and you can decide whether you want to use that text, or correct > my mistakes. > > apm,sata-speed : Tx operating speed for SATA mode. A 3-tuple for each > supported link speed on the host, with a bit mask of > compatible device speeds, encoded as > 0x0001 - SATA-I (1.5gbits/s) > 0x0002 - SATA-II (3.0gbits/s) > 0x0004 - SATA-6G (6.0gbits/s) > Default is <0x1 0x3 0x7>. > I got it. Why not stay with unit of Kbps and let the driver handle the conversion? -Loc
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene-phy.txt b/Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file mode 100644 index 0000000..3cbfa75 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/apm-xgene-phy.txt @@ -0,0 +1,89 @@ +* APM X-Gene 15Gbps Multi-purpose PHY nodes + +PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each +PHY (pair of lanes) has its own node. + +Required properties: +- compatible : Shall be "apm,xgene-phy" or + "apm,xgene-phy-ext". The "apm,xgene-phy" describes + an PHY with internal reference PLL located within + the IP. The "apm,xgene-phy-ext" describes an PHY + where the internal reference PLL located outside of + the IP. +- reg : First PHY memory resource is the SDS PHY access + resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext". +- #phy-cells : Shall be 1 as it expects one argument for setting + the mode of the PHY. Possible values are 0 (SATA), + 1 (SGMII), 2 (PCIe), or 3 (USB). + +Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa. +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample + data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Default is 0x0. +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf. +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. +- apm,tx-speed : Tx operating speed. One set of 3-tuple for + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7. + +NOTE: PHY override parameters are board specific setting. + +Example: + phy1: phy@1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>, + <0x0 0x1f21c000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + apm,tx-boost-gain = <0x2 0x2 0x2 0x2 0x2 0x2>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0xa 0xa 0xa>; + }; + + phy2: phy@1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>, + <0x0 0x1f22c000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x2 0x2 0x2 0x2 0x2 0x2>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0x5 0x5 0x5>; + }; + + phy3: phy@1f23a000 { + compatible = "apm,xgene-phy-ext"; + reg = <0x0 0x1f23a000 0x0 0x100>, + <0x0 0x1f23c000 0x0 0x100>, + <0x0 0x1f2d0000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x3 0x3 0x3 0x3 0x3 0x3>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0xc 0xc 0xc>; + };