From patchwork Thu Dec 12 20:30:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3334351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0D253C0D4A for ; Thu, 12 Dec 2013 21:09:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 254F7207D1 for ; Thu, 12 Dec 2013 21:09:55 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DEB4B207E0 for ; Thu, 12 Dec 2013 21:09:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VrDUU-0005o5-0J; Thu, 12 Dec 2013 21:08:14 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VrDU8-0001xI-6t; Thu, 12 Dec 2013 21:07:52 +0000 Received: from va3ehsobe010.messaging.microsoft.com ([216.32.180.30] helo=va3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VrDTT-0001rR-HX for linux-arm-kernel@lists.infradead.org; Thu, 12 Dec 2013 21:07:15 +0000 Received: from mail22-va3-R.bigfish.com (10.7.14.235) by VA3EHSOBE010.bigfish.com (10.7.40.12) with Microsoft SMTP Server id 14.1.225.22; Thu, 12 Dec 2013 21:06:50 +0000 Received: from mail22-va3 (localhost [127.0.0.1]) by mail22-va3-R.bigfish.com (Postfix) with ESMTP id AA67A3400D6; Thu, 12 Dec 2013 21:06:50 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 11 X-BigFish: VS11(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h286p1155h) Received-SPF: pass (mail22-va3: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=dinguyen@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail22-va3 (localhost.localdomain [127.0.0.1]) by mail22-va3 (MessageSwitch) id 1386882408384516_29800; Thu, 12 Dec 2013 21:06:48 +0000 (UTC) Received: from VA3EHSMHS030.bigfish.com (unknown [10.7.14.247]) by mail22-va3.bigfish.com (Postfix) with ESMTP id 4BF2C3E005B; Thu, 12 Dec 2013 21:06:48 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by VA3EHSMHS030.bigfish.com (10.7.99.40) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 12 Dec 2013 21:06:47 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Thu, 12 Dec 2013 12:58:17 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id e063HToQ010208; Wed, 5 Jan 2000 19:17:37 -0800 (PST) From: To: , , , , , , , , , , , , , Subject: [PATCHv6 3/5] dts: socfpga: Add support for SD/MMC on the SOCFPGA platform Date: Thu, 12 Dec 2013 14:30:43 -0600 Message-ID: <1386880245-10192-4-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386880245-10192-1-git-send-email-dinguyen@altera.com> References: <1386880245-10192-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131212_160711_731882_25B3C1E0 X-CRM114-Status: GOOD ( 14.88 ) X-Spam-Score: -2.6 (--) Cc: zhangfei.gao@linaro.org, linux-mmc@vger.kernel.org, Dinh Nguyen , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Adds a new binding, "altr,socfpga-sdmmc-sdr-clk". This is a new clock binding that the SD/MMC driver can use the common clock framework to set the appropriate clock phase shift settings for the CIU clock. Also add the "syscon" binding to the "altr,sys-mgr" node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock phase shift settings. Signed-off-by: Dinh Nguyen --- v6: Add documentation for "altr,socfpga-sdmmc-sdr-clk". Add "syscon" to the sysmgr binding. v5: Use the "snps,dw-mshc" binding v4: Re-use "rockchip,rk2928-dw-mshc" binding v3: none v2: none --- .../devicetree/bindings/clock/altr_socfpga.txt | 11 +++++++++-- arch/arm/boot/dts/socfpga.dtsi | 19 ++++++++++++++++++- arch/arm/boot/dts/socfpga_arria5.dtsi | 12 ++++++++++++ arch/arm/boot/dts/socfpga_cyclone5.dtsi | 12 ++++++++++++ arch/arm/boot/dts/socfpga_vt.dts | 12 ++++++++++++ 5 files changed, 63 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 0045433..a2e75f0 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -11,10 +11,17 @@ Required properties: PLL clock. "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and can get gated. + "altr,socfpga-sdmmc-sdr-clk" - Clock that controls the SD/MMC SDR phase + shift settings for the SD/MMC -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. +- reg : shall be one of the following: + * For the "altr,socfpga-sdmmc-sdr-clk" clock, reg will the register + offset that controls the SD/MMC SDR phase shift settings. + * For all of the other clocks, control register offset from + CLOCK_MANAGER's base for the clock. - clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. + either an oscillator or a pll output. This is an optional field for + the "altr,socfpga-sdmmc-sdr-clk" clock. - #clock-cells : from common clock binding, shall be set to 0. Optional properties: diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..4be9aaf 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -436,6 +436,12 @@ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; clk-gate = <0xa0 11>; }; + + sdr_mmc_clk: sdr_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-sdmmc-sdr-clk"; + reg = <0x108>; + }; }; }; @@ -469,6 +475,17 @@ cache-level = <2>; }; + mmc: dwmmc0@ff704000 { + compatible = "snps,dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>, <&sdr_mmc_clk>; + clock-names = "biu", "ciu", "sdr_mmc_clk"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; @@ -523,7 +540,7 @@ }; sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x4000>; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index a85b404..112b7e2 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -27,6 +27,18 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <0 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + serial0@ffc02000 { clock-frequency = <100000000>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index a8716f6..52b1501 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,6 +28,18 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <0 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index d1ec0ca..9e93768 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -41,6 +41,18 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + samsung,dw-mshc-sdr-timing = <0 3>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff700000 { phy-mode = "gmii"; status = "okay";