From patchwork Mon Dec 16 13:01:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Yanovich X-Patchwork-Id: 3354101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 78356C0D4A for ; Mon, 16 Dec 2013 13:02:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 43B8020119 for ; Mon, 16 Dec 2013 13:02:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BCB320115 for ; Mon, 16 Dec 2013 13:02:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsXo7-0004UB-IC; Mon, 16 Dec 2013 13:01:59 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsXo5-0002at-4J; Mon, 16 Dec 2013 13:01:57 +0000 Received: from mail-lb0-x22b.google.com ([2a00:1450:4010:c04::22b]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsXo1-0002Zu-SU for linux-arm-kernel@lists.infradead.org; Mon, 16 Dec 2013 13:01:55 +0000 Received: by mail-lb0-f171.google.com with SMTP id w7so832729lbi.2 for ; Mon, 16 Dec 2013 05:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:subject:from:to:cc:date:in-reply-to:references :content-type:mime-version:content-transfer-encoding; bh=p2ujHcNLfXT/BhdiFlE9reAFFULXjJy+BioMKsl84W8=; b=dURqOzY66ai2B1Nn0De4Zf4JR+kr8jR11qbJj8RidJSdQKOMWa+8j+gx8gmfZ1EWlk hzvmXSNkeEviJZUL3K0KRooqnIAoXxz2CoapdqZrdiTNudkHzyp6tFHMmP5e89n97evP MUvPinKG+kD+i2FHPkHWtcOjRhAYV+uA4LOSoKjfP/Q+Jwy+Ps5njRGWJqt/uUPY/UcE NxeecFTcDiXRS6i7hUWHAqzzh9RphIl0YSy+8W9PTZ/UUd0S8eBb51oSK+++MNw0aRma cRSZ5WXLWYOstTFzeuJvCvC2nWrXNL6qN6EhG/oxrJCvLXAZBSpCUq4J6oGWRR+zYuoT xSvQ== X-Received: by 10.152.5.8 with SMTP id o8mr170325lao.89.1387198889132; Mon, 16 Dec 2013 05:01:29 -0800 (PST) Received: from [192.168.1.5] (0893675324.static.corbina.ru. [95.31.1.192]) by mx.google.com with ESMTPSA id n13sm9517592lbl.17.2013.12.16.05.01.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 16 Dec 2013 05:01:28 -0800 (PST) Message-ID: <1387198885.13062.154.camel@host5.omatika.ru> Subject: Re: [PATCH v2 00/16] ARM: support for ICP DAS LP-8x4x (with dts) From: Sergei Ianovich To: Arnd Bergmann Date: Mon, 16 Dec 2013 17:01:25 +0400 In-Reply-To: <201312150355.27755.arnd@arndb.de> References: <1386543229-1542-1-git-send-email-ynvich@gmail.com> <201312150153.54044.arnd@arndb.de> <1387073571.13062.102.camel@host5.omatika.ru> <201312150355.27755.arnd@arndb.de> X-Mailer: Evolution 3.8.5-2+b1 Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131216_080154_271731_E8489379 X-CRM114-Status: GOOD ( 15.83 ) X-Spam-Score: -1.9 (-) Cc: Haojian Zhuang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Mack X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SBL, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Sun, 2013-12-15 at 03:55 +0100, Arnd Bergmann wrote: > On Sunday 15 December 2013, Sergei Ianovich wrote: > ... > I think the way you have structured your code is good, and an MFD would > not help. Please just restructure the DT representation to contain the > external-bus and/or the fpga connected to it. You probably don't need both, > but it doesn't hurt to show them as different device-nodes either. > Your choice. PXA27x memory bus can have up to 10 devices: up to 6 slower flash/SRAM/variable-latency-IO selected by nCS<0> to <5>, and up to 4 partions of SDRAM selected by nSDCS<0> to <3>. It appears that the FPGA is directly connected to the memory bus and is selected by nCS<5>. According to MSC2 configuration (already in the mainstream U-Boot), the FPGA is configured as a synchronous SRAM with access cycle of 30x memory bus cycles. So I made it a top-level bus like pxabus. Ethernet devices are also connected to the memory bus via some kind of gate array. This one is a bit faster -- 15x memory cycles, which is still a lot. It explains why network transfers are never faster than 15 Mbit/s. The final tree looks like this: diff --git a/arch/arm/boot/dts/pxa27x-lp8x4x.dts b/arch/arm/boot/dts/pxa27x-lp8x4x.dts new file mode 100644 index 0000000..cb2a31d --- /dev/null +++ b/arch/arm/boot/dts/pxa27x-lp8x4x.dts @@ -0,0 +1,208 @@ +/* Device tree for ICP DAS LP-8x4x */ +/dts-v1/; + +#include +#include "pxa27x.dtsi" + +/ { + model = "ICP DAS LP-8x4x programmable automation controller"; + compatible = "marvell,lp8x4x", "marvell,pxa270"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + + memory { + /* + * SDRAM + * connected to CPU via nSDCS<0> + */ + reg = <0xa0000000 0x08000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vmmc: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + flash@00000000 { + /* + * Boot memory + * connected to CPU via nCS<0> + */ + compatible = "cfi-flash"; + reg = <0x0 0x02000000>; + bank-width = <4>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + fs@0 { + label = "u-boot"; + reg = <0 0x40000>; + }; + fs@40000 { + label = "settings"; + reg = <0x40000 0x40000>; + }; + fs@80000 { + label = "kernel"; + reg = <0x80000 0x280000>; + }; + fs@300000 { + label = "root_fs"; + reg = <0x300000 0x1d00000>; + }; + }; + + flash@04000000 { + /* + * connected to CPU via nCS<1> + */ + compatible = "cfi-flash"; + reg = <0x04000000 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + + pxabus { + pxairq: interrupt-controller@40d00000 { + marvell,intc-priority; + marvell,intc-nr-irqs = <34>; + }; + + uart@40100000 { + status = "okay"; + }; + + uart@40200000 { + status = "okay"; + }; + + uart@40700000 { + status = "okay"; + }; + + mmc@41100000 { + status = "okay"; + vmmc-supply = <&vmmc>; + }; + + ohci@4c000000 { + status = "okay"; + marvell,port-mode = <3>; + marvell,oc-mode-perport; + marvell,enable-port1; + }; + }; + + extbus { + /* + * Transparent bus, 2 byte-wide access + * connected to CPU via nCS<3> + */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gpio>; + + eth0: eth@0c000000 { + compatible = "davicom,dm9000"; + reg = <0x0c000000 0x2 + 0x0c004000 0x2>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + status = "okay"; + }; + + eth1: eth@0d000000 { + compatible = "davicom,dm9000"; + reg = <0x0d000000 0x2 + 0x0d004000 0x2>; + interrupts = <82 IRQ_TYPE_EDGE_RISING>; + status = "okay"; + }; + }; + + fpgabus { + /* + * Transparent bus, 1 byte-wide access, even addresses only + * connected to CPU via nCS<5> + */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x17000000 0x10000>; + interrupt-parent = <&fpga>; + + rtc@901c { + compatible = "ds,rtc-ds1302"; + reg = <0x901c 0x1>; + status = "okay"; + }; + + sram@a000 { + compatible = "icpdas,sram-lp8x4x"; + reg = <0xa000 0x1000 + 0x901e 0x1>; + }; + + fpga: irq@9006 { + compatible = "icpdas,irq-lp8x4x"; + reg = <0x9006 0x16>; + interrupt-parent = <&gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + #interrupt-cells = <1>; + interrupt-controller; + status = "okay"; + }; + + uart@9050 { + compatible = "icpdas,uart-lp8x4x"; + reg = <0x9050 0x10 + 0x9030 0x02>; + interrupts = <13>; + status = "okay"; + }; + + uart@9060 { + compatible = "icpdas,uart-lp8x4x"; + reg = <0x9060 0x10 + 0x9032 0x02>; + interrupts = <14>; + status = "okay"; + }; + + uart@9070 { + compatible = "icpdas,uart-lp8x4x"; + reg = <0x9070 0x10 + 0x9034 0x02>; + interrupts = <15>; + status = "okay"; + }; + + backplane@9046 { + compatible = "icpdas,backplane-lp8x4x"; + reg = <0x9046 0x2 + 0x9004 0x2 + 0x1000 0x10 + 0x2000 0x10 + 0x3000 0x10 + 0x4000 0x10 + 0x5000 0x10 + 0x6000 0x10 + 0x7000 0x10 + 0x8000 0x10>; + }; + }; +};