@@ -31,6 +31,12 @@
#define COMPAT_HWCAP_IDIVT (1 << 18)
#define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT)
#define COMPAT_HWCAP_EVTSTRM (1 << 21)
+#define COMPAT_HWCAP_EVTSTRM (1 << 21)
+#define COMPAT_HWCAP_AES (1 << 22)
+#define COMPAT_HWCAP_PMULL (1 << 23)
+#define COMPAT_HWCAP_SHA1 (1 << 24)
+#define COMPAT_HWCAP_SHA2 (1 << 25)
+#define COMPAT_HWCAP_CRC32 (1 << 26)
#ifndef __ASSEMBLY__
/*
@@ -168,6 +168,38 @@ static void __init setup_processor(void)
block = (features >> 16) & 0xf;
if (block && !(block & 0x8))
elf_hwcap |= HWCAP_CRC32;
+
+#ifdef CONFIG_COMPAT
+ /*
+ * ID_ISAR5_EL1 carries similar information as above, but pertaining to
+ * the Aarch32 32-bit execution state.
+ */
+ features = read_cpuid(ID_ISAR5_EL1);
+ block = (features >> 4) & 0xf;
+ if (!(block & 0x8)) {
+ switch (block) {
+ default:
+ case 2:
+ compat_elf_hwcap |= COMPAT_HWCAP_PMULL;
+ case 1:
+ compat_elf_hwcap |= COMPAT_HWCAP_AES;
+ case 0:
+ break;
+ }
+ }
+
+ block = (features >> 8) & 0xf;
+ if (block && !(block & 0x8))
+ compat_elf_hwcap |= COMPAT_HWCAP_SHA1;
+
+ block = (features >> 12) & 0xf;
+ if (block && !(block & 0x8))
+ compat_elf_hwcap |= COMPAT_HWCAP_SHA2;
+
+ block = (features >> 16) & 0xf;
+ if (block && !(block & 0x8))
+ compat_elf_hwcap |= COMPAT_HWCAP_CRC32;
+#endif
}
static void __init setup_machine_fdt(phys_addr_t dt_phys)
The ARMv8 Crypto Extensions may also be available to userland processes running in 32-bit mode. Allocate the compat bits and set them at boot. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- arch/arm64/include/asm/hwcap.h | 6 ++++++ arch/arm64/kernel/setup.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)