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[82.169.5.66]) by mx.google.com with ESMTPSA id fj8sm46381851wib.1.2013.12.16.13.05.05 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Dec 2013 13:05:06 -0800 (PST) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, steve.capper@linaro.org Subject: [PATCH 4/4] arm64: add 32-bit compat hwcaps for v8 crypto extensions Date: Mon, 16 Dec 2013 22:04:38 +0100 Message-Id: <1387227878-30438-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1387227878-30438-1-git-send-email-ard.biesheuvel@linaro.org> References: <1387227878-30438-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131216_160529_643367_9D72A43A X-CRM114-Status: GOOD ( 11.53 ) X-Spam-Score: -2.6 (--) Cc: Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ARMv8 Crypto Extensions may also be available to userland processes running in 32-bit mode. Allocate the compat bits and set them at boot. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/hwcap.h | 6 ++++++ arch/arm64/kernel/setup.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 6cddbb0..4ae8c69 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -31,6 +31,12 @@ #define COMPAT_HWCAP_IDIVT (1 << 18) #define COMPAT_HWCAP_IDIV (COMPAT_HWCAP_IDIVA|COMPAT_HWCAP_IDIVT) #define COMPAT_HWCAP_EVTSTRM (1 << 21) +#define COMPAT_HWCAP_EVTSTRM (1 << 21) +#define COMPAT_HWCAP_AES (1 << 22) +#define COMPAT_HWCAP_PMULL (1 << 23) +#define COMPAT_HWCAP_SHA1 (1 << 24) +#define COMPAT_HWCAP_SHA2 (1 << 25) +#define COMPAT_HWCAP_CRC32 (1 << 26) #ifndef __ASSEMBLY__ /* diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 961c961..283039d 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -168,6 +168,38 @@ static void __init setup_processor(void) block = (features >> 16) & 0xf; if (block && !(block & 0x8)) elf_hwcap |= HWCAP_CRC32; + +#ifdef CONFIG_COMPAT + /* + * ID_ISAR5_EL1 carries similar information as above, but pertaining to + * the Aarch32 32-bit execution state. + */ + features = read_cpuid(ID_ISAR5_EL1); + block = (features >> 4) & 0xf; + if (!(block & 0x8)) { + switch (block) { + default: + case 2: + compat_elf_hwcap |= COMPAT_HWCAP_PMULL; + case 1: + compat_elf_hwcap |= COMPAT_HWCAP_AES; + case 0: + break; + } + } + + block = (features >> 8) & 0xf; + if (block && !(block & 0x8)) + compat_elf_hwcap |= COMPAT_HWCAP_SHA1; + + block = (features >> 12) & 0xf; + if (block && !(block & 0x8)) + compat_elf_hwcap |= COMPAT_HWCAP_SHA2; + + block = (features >> 16) & 0xf; + if (block && !(block & 0x8)) + compat_elf_hwcap |= COMPAT_HWCAP_CRC32; +#endif } static void __init setup_machine_fdt(phys_addr_t dt_phys)