From patchwork Mon Dec 16 21:25:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 3356991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 83031C0D4A for ; Mon, 16 Dec 2013 21:26:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7FE6A2024D for ; Mon, 16 Dec 2013 21:26:53 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86AF22024C for ; Mon, 16 Dec 2013 21:26:52 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsfgR-0000ga-2F; Mon, 16 Dec 2013 21:26:35 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsfgK-00074v-27; Mon, 16 Dec 2013 21:26:28 +0000 Received: from mo1.mail-out.ovh.net ([178.32.228.1]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsfgH-00073w-1k for linux-arm-kernel@lists.infradead.org; Mon, 16 Dec 2013 21:26:25 +0000 Received: from mail436.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo1.mail-out.ovh.net (Postfix) with SMTP id 37D68FFAB4E for ; Mon, 16 Dec 2013 22:29:40 +0100 (CET) Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 16 Dec 2013 23:26:48 +0200 Received: from cha74-5-78-236-240-82.fbx.proxad.net (HELO localhost.localdomain) (b.brezillon@overkiz.com@78.236.240.82) by ns0.ovh.net with SMTP; 16 Dec 2013 23:26:47 +0200 From: Boris BREZILLON To: Rob Landley , Nicolas Ferre , Jean-Christophe Plagniol-Villard , Russell King , Thomas Gleixner , Grant Likely Subject: [RFC PATCH 10/10] ARM: at91/dt: add new AIC irq mux definitions for sama5 SoCs Date: Mon, 16 Dec 2013 22:25:40 +0100 Message-Id: <1387229140-7642-1-git-send-email-b.brezillon@overkiz.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387225461-6201-1-git-send-email-b.brezillon@overkiz.com> References: <1387225461-6201-1-git-send-email-b.brezillon@overkiz.com> X-Ovh-Tracer-Id: 8071013482370791522 X-Ovh-Remote: 78.236.240.82 (cha74-5-78-236-240-82.fbx.proxad.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-OVH-SPAMSTATE: OK X-OVH-SPAMSCORE: -100 X-OVH-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeiledrleeiucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-Spam-Check: DONE|U 0.5/N X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeiledrleeiucetufdoteggodetrfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131216_162625_271164_FB692454 X-CRM114-Status: GOOD ( 13.50 ) X-Spam-Score: -1.9 (-) Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Boris BREZILLON X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add irq line muxing definition for sama5 SoCs. Signed-off-by: Boris BREZILLON --- arch/arm/boot/dts/sama5d3.dtsi | 40 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/sama5d3_tcb1.dtsi | 22 +++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index de9fece..1e8f4b5 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -390,6 +390,44 @@ interrupt-controller; reg = <0xfffff000 0x200>; atmel,external-irqs = <47>; + #address-cells = <1>; + #size-cells = <0>; + atmel,aic-irq-mapping = <0xffffffff 0x7ffff>; + + sysc_irq_mux: irq-mux@1 { + compatible = "atmel,aic-mux"; + reg = <1>; + + pmc_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&pmc 0 0x64 0x5074b>; + }; + + rtc_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&rtc 0 0x24 0x1f>; + }; + }; + + tcb0_irq_mux: irq-mux@26 { + compatible = "atmel,aic-mux"; + reg = <26>; + + tc0_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb0 0 0x28 0xff>; + }; + + tc1_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb0 0 0x68 0xff>; + }; + + tc2_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb0 0 0xa8 0xff>; + }; + }; }; pinctrl@fffff200 { @@ -1061,7 +1099,7 @@ status = "disabled"; }; - rtc@fffffeb0 { + rtc: rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 382b044..123b153 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -18,6 +18,28 @@ ahb { apb { + aic: interrupt-controller@fffff000 { + tcb1_irq_mux: irq-mux@27 { + compatible = "atmel,aic-mux"; + reg = <27>; + + tc3_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb1 0 0x28 0xff>; + }; + + tc4_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb1 0 0x68 0xff>; + }; + + tc5_irq { + compatible = "atmel,aic-mux-3reg-irq"; + atmel,aic-mux-irq-reg = <&tcb1 0 0xa8 0xff>; + }; + }; + }; + pmc: pmc@fffffc00 { periphck { tcb1_clk: tcb1_clk {