From patchwork Tue Dec 17 09:26:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 3359981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A83D69F314 for ; Tue, 17 Dec 2013 09:29:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8DD6120398 for ; Tue, 17 Dec 2013 09:29:49 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFDBA20397 for ; Tue, 17 Dec 2013 09:29:44 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vsqws-0003Ba-TV; Tue, 17 Dec 2013 09:28:19 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VsqwT-0006GW-ES; Tue, 17 Dec 2013 09:27:53 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vsqvu-0006CI-4b for linux-arm-kernel@lists.infradead.org; Tue, 17 Dec 2013 09:27:20 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 17 Dec 2013 01:27:00 -0800 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 17 Dec 2013 01:29:14 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 17 Dec 2013 01:29:14 -0800 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Tue, 17 Dec 2013 01:26:58 -0800 From: Joseph Lo To: Stephen Warren , Thierry Reding , Peter De Schrijver Subject: [PATCH 4/4] clk: tegra20: enable EMC clock driver Date: Tue, 17 Dec 2013 17:26:40 +0800 Message-ID: <1387272400-4689-5-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.5 In-Reply-To: <1387272400-4689-1-git-send-email-josephl@nvidia.com> References: <1387272400-4689-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131217_042718_328370_85E9259A X-CRM114-Status: GOOD ( 11.07 ) X-Spam-Score: -2.4 (--) Cc: linux-tegra@vger.kernel.org, Mike Turquette , linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Re-register the EMC clock to the EMC clock driver in the Tegra CCF driver to support EMC scaling. Signed-off-by: Joseph Lo --- Cc: Mike Turquette --- drivers/clk/tegra/clk-tegra20.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dbace152b2fa..ecae0f6bb7bf 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -795,6 +795,20 @@ static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), }; +static struct tegra_clk_periph tegra_emc_periph = + TEGRA_CLK_PERIPH(30, 3, 0, 0, 8, 1, 0, TEGRA20_CLK_EMC, 0, NULL, NULL); + +static __init void tegra20_emc_clk_init(void __iomem *clk_base) +{ + struct clk *clk; + + clk = tegra_clk_register_emc("emc", mux_pllmcp_clkm, + ARRAY_SIZE(mux_pllmcp_clkm), &tegra_emc_periph, clk_base, + CLK_SOURCE_EMC, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE); + + clks[TEGRA20_CLK_EMC] = clk; +} + static void __init tegra20_periph_clk_init(void) { struct tegra_periph_init_data *data; @@ -812,16 +826,6 @@ static void __init tegra20_periph_clk_init(void) 0, 34, periph_clk_enb_refcnt); clks[TEGRA20_CLK_APBDMA] = clk; - /* emc */ - clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), - CLK_SET_RATE_NO_REPARENT, - clk_base + CLK_SOURCE_EMC, - 30, 2, 0, NULL); - clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, - 57, periph_clk_enb_refcnt); - clks[TEGRA20_CLK_EMC] = clk; - /* dsi */ clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 48, periph_clk_enb_refcnt); @@ -1114,6 +1118,7 @@ static void __init tegra20_clock_init(struct device_node *np) tegra20_super_clk_init(); tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); tegra20_periph_clk_init(); + tegra20_emc_clk_init(clk_base); tegra20_audio_clk_init(); tegra_pmc_clk_init(pmc_base, tegra20_clks);