From patchwork Tue Dec 17 19:37:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Yanovich X-Patchwork-Id: 3364701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 85A7CC0D4A for ; Tue, 17 Dec 2013 19:43:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3133B203A9 for ; Tue, 17 Dec 2013 19:43:38 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E7A620270 for ; Tue, 17 Dec 2013 19:43:36 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vt0Y4-0003xU-Bc; Tue, 17 Dec 2013 19:43:20 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vt0Y0-0008Eg-BG; Tue, 17 Dec 2013 19:43:16 +0000 Received: from mail-la0-x229.google.com ([2a00:1450:4010:c03::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vt0VP-0007xx-8s for linux-arm-kernel@lists.infradead.org; Tue, 17 Dec 2013 19:40:42 +0000 Received: by mail-la0-f41.google.com with SMTP id eo20so3447828lab.14 for ; Tue, 17 Dec 2013 11:40:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l2Sy9hX6nJLQwieWcNECp6SCWNRpBKojwL0jk+/HYc0=; b=x61lsZqwIdAaT4c7kMHKQlWQN52+YY5iZJE0Q8j59A7uKfixfT6FCrrfjGKjD5xyLS ZvJzO6wRFFY3OO20Ise3VtDyI4iujy+Rp9KTZ4pYl5jCY3EuITkEVJsOliW9FHTmLQ+F kKJ0qGo7MuM1kExeo9qbjr1tl4QBEjCfLI+PTafUyC36QQsmWjOAqQpOVyCXLiLdC/CS Tho1gfyFGA6DDLOyZVcfYxO6DUvVqkg73WvPHNynJ+1vIQqT9YJtFdabIMileTEgBmoi eEFf8lnO1ZcJcRP2SCrTf19s/ShwtVMUOdL3uXxwx87BVbREqyzPySO+IkDfqFX/V2Br SJpw== X-Received: by 10.112.141.67 with SMTP id rm3mr291237lbb.31.1387309213549; Tue, 17 Dec 2013 11:40:13 -0800 (PST) Received: from host5.omatika.ru (0893675324.static.corbina.ru. [95.31.1.192]) by mx.google.com with ESMTPSA id dw1sm2299009lbc.4.2013.12.17.11.40.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Dec 2013 11:40:12 -0800 (PST) From: Sergei Ianovich To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 16/21] misc: support for writing to LP-8x4x EEPROM Date: Tue, 17 Dec 2013 23:37:46 +0400 Message-Id: <1387309071-22382-17-git-send-email-ynvich@gmail.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1387309071-22382-1-git-send-email-ynvich@gmail.com> References: <1386901645-28895-1-git-send-email-ynvich@gmail.com> <1387309071-22382-1-git-send-email-ynvich@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131217_144035_544533_C7589A80 X-CRM114-Status: GOOD ( 17.04 ) X-Spam-Score: -1.9 (-) Cc: Mark Rutland , "open list:OPEN FIRMWARE AND..." , Russell King , Arnd Bergmann , Pawel Moll , Ian Campbell , Greg Kroah-Hartman , "open list:DOCUMENTATION" , Rob Herring , Sergei Ianovich , Rob Landley , Kumar Gala X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SBL, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP at24c128 write protection is implemented by a separate GPIO line. EEPROM driver doesn't provide this option, so we implement it in the board-specific device. Signed-off-by: Sergei Ianovich --- v2..v3 * new patch .../devicetree/bindings/misc/lp8x4x-bus.txt | 3 ++ Documentation/misc-devices/lp8x4x_bus.txt | 3 ++ arch/arm/boot/dts/pxa27x-lp8x4x.dts | 1 + drivers/misc/lp8x4x_bus.c | 50 ++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/lp8x4x-bus.txt b/Documentation/devicetree/bindings/misc/lp8x4x-bus.txt index 1b1776a..b0fb145 100644 --- a/Documentation/devicetree/bindings/misc/lp8x4x-bus.txt +++ b/Documentation/devicetree/bindings/misc/lp8x4x-bus.txt @@ -10,6 +10,8 @@ Required properties: * the 8bit DIP switch * the slot count register +- eeprom-gpios : should point to active-low write enable GPIO + Example: backplane { @@ -17,4 +19,5 @@ Example: reg = <0x0 0x2 0x9002 0x2 0x9046 0x2>; + eeprom-gpios = <&gpio 4 0>; }; diff --git a/Documentation/misc-devices/lp8x4x_bus.txt b/Documentation/misc-devices/lp8x4x_bus.txt index 829781b..78ea0a89 100644 --- a/Documentation/misc-devices/lp8x4x_bus.txt +++ b/Documentation/misc-devices/lp8x4x_bus.txt @@ -29,6 +29,9 @@ SYSFS dip RO - shows status of LP-8x4x 8bit DIP switch +eeprom_write_enable + RW - controls write access to board's EEPROM (1 - enable) + rotary RO - shows position of LP-8x4x rotary switch (0-9) diff --git a/arch/arm/boot/dts/pxa27x-lp8x4x.dts b/arch/arm/boot/dts/pxa27x-lp8x4x.dts index 09a6bc9..52f0036 100644 --- a/arch/arm/boot/dts/pxa27x-lp8x4x.dts +++ b/arch/arm/boot/dts/pxa27x-lp8x4x.dts @@ -208,6 +208,7 @@ reg = <0x0 0x2 0x9002 0x2 0x9046 0x2>; + eeprom-gpios = <&gpio 4 0>; }; }; }; diff --git a/drivers/misc/lp8x4x_bus.c b/drivers/misc/lp8x4x_bus.c index dfbc8c4..567fe078 100644 --- a/drivers/misc/lp8x4x_bus.c +++ b/drivers/misc/lp8x4x_bus.c @@ -9,6 +9,7 @@ * published by the Free Software Foundation or any later version. */ #include +#include #include #include #include @@ -27,6 +28,7 @@ struct lp8x4x_master { void *count_addr; void *rotary_addr; void *dip_addr; + struct gpio_desc *eeprom_nWE; struct device dev; }; @@ -68,6 +70,40 @@ static ssize_t rotary_show(struct device *dev, static DEVICE_ATTR_RO(rotary); +static ssize_t eeprom_write_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct lp8x4x_master *m = container_of(dev, struct lp8x4x_master, dev); + + return sprintf(buf, "%u\n", !gpiod_get_value(m->eeprom_nWE)); +} + +static ssize_t eeprom_write_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct lp8x4x_master *m = container_of(dev, struct lp8x4x_master, dev); + unsigned int val = 0; + int err; + + if (!buf) + return count; + + if (0 == count) + return count; + + err = kstrtouint(buf, 10, &val); + if (err != 0) { + dev_err(dev, "Bad input %s\n", buf); + return count; + } + + gpiod_set_value(m->eeprom_nWE, !val); + + return count; +} + +static DEVICE_ATTR_RW(eeprom_write_enable); + static ssize_t dip_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -81,6 +117,7 @@ static DEVICE_ATTR_RO(dip); static struct attribute *master_dev_attrs[] = { &dev_attr_slot_count.attr, &dev_attr_rotary.attr, + &dev_attr_eeprom_write_enable.attr, &dev_attr_dip.attr, NULL, }; @@ -156,6 +193,19 @@ static int __init lp8x4x_bus_probe(struct platform_device *pdev) goto err_free; } + m->eeprom_nWE = devm_gpiod_get(&pdev->dev, "eeprom"); + if (IS_ERR(m->eeprom_nWE)) { + err = PTR_ERR(m->eeprom_nWE); + dev_err(&pdev->dev, "Failed to get eeprom GPIO\n"); + goto err_free; + } + + err = gpiod_direction_output(m->eeprom_nWE, 1); + if (err < 0) { + dev_err(&pdev->dev, "Failed to set eeprom GPIO output\n"); + goto err_free; + } + m->slot_count = ioread8(m->count_addr); switch (m->slot_count) { case 1: