| Message ID | 1387468774-14216-6-git-send-email-treding@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12/19/2013 08:59 AM, Thierry Reding wrote: > Add device tree nodes for the DSI controllers found on Tegra114 SoCs. > diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi > + dsi@54300000 { > + compatible = "nvidia,tegra114-dsi"; > + reg = <0x54300000 0x00040000>; > + clocks = <&tegra_car TEGRA114_CLK_DSIA>, > + <&tegra_car TEGRA114_CLK_DSIALP>, > + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; > + clock-names = "dsi", "lp", "parent"; The binding document Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt doesn't mention an "lp" clock: - clock-names: Must include the following entries: - dsi This MUST be the first entry. - parent I assume this is simply an oversight, since this is an obvious extension of the binding, and that the DT binding will be updated to include that clock in the list, and hence won't block applying the series because of this.
On Thu, Dec 19, 2013 at 12:57:54PM -0700, Stephen Warren wrote: > On 12/19/2013 08:59 AM, Thierry Reding wrote: > > Add device tree nodes for the DSI controllers found on Tegra114 SoCs. > > > diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi > > > + dsi@54300000 { > > + compatible = "nvidia,tegra114-dsi"; > > + reg = <0x54300000 0x00040000>; > > + clocks = <&tegra_car TEGRA114_CLK_DSIA>, > > + <&tegra_car TEGRA114_CLK_DSIALP>, > > + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; > > + clock-names = "dsi", "lp", "parent"; > > The binding document > Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt doesn't > mention an "lp" clock: > > - clock-names: Must include the following entries: > - dsi > This MUST be the first entry. > - parent > > I assume this is simply an oversight, since this is an obvious extension > of the binding, and that the DT binding will be updated to include that > clock in the list, and hence won't block applying the series because of > this. Yes, that was merely an oversight. I've updated the DT binding to include the lp clock. Thanks, Thierry
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 65e34e7fe6f2..28d2eea46b52 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -71,6 +71,38 @@ reset-names = "hdmi"; status = "disabled"; }; + + dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; gic: interrupt-controller@50041000 {
Add device tree nodes for the DSI controllers found on Tegra114 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v4: - add reset and reset-names properties Changes in v3: - add #address-cells and #size-cells properties for DSI bus - update for revised MIPI calibration bindings - add low-power clocks Changes in v2: - use a comment to describe which pads need calibration arch/arm/boot/dts/tegra114.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)