From patchwork Fri Dec 20 16:34:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 3390171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C563EC0D4A for ; Fri, 20 Dec 2013 17:13:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 98876204CF for ; Fri, 20 Dec 2013 17:13:16 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D7AD204A2 for ; Fri, 20 Dec 2013 17:13:15 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vu35O-0002M1-IM; Fri, 20 Dec 2013 16:38:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vu34U-0000sk-NN; Fri, 20 Dec 2013 16:37:06 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vu32v-0000dG-CS for linux-arm-kernel@lists.infradead.org; Fri, 20 Dec 2013 16:35:32 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id rBKGZBnc023428; Fri, 20 Dec 2013 10:35:11 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBKGZBWM008897; Fri, 20 Dec 2013 10:35:11 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Fri, 20 Dec 2013 10:35:10 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id rBKGYh6d031953; Fri, 20 Dec 2013 10:35:08 -0600 From: Tero Kristo To: , , , , , , Subject: [PATCHv12 09/49] clk: mux: add support for low level ops Date: Fri, 20 Dec 2013 18:34:27 +0200 Message-ID: <1387557274-22583-9-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387557274-22583-1-git-send-email-t-kristo@ti.com> References: <1387557274-22583-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131220_113529_685175_43BE060C X-CRM114-Status: GOOD ( 11.84 ) X-Spam-Score: -7.4 (-------) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Multiplexer clock can now be registered to use low level register access ops. Preferred initialization method is via clock description. Signed-off-by: Tero Kristo --- drivers/clk/clk-mux.c | 24 +++++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 2cbed08..ed3bc36 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -46,7 +46,12 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so * val = 0x4 really means "bit 2, index starts at bit 0" */ - val = clk_readl(mux->reg) >> mux->shift; + if (mux->ll_ops) + val = mux->ll_ops->clk_readl(mux->reg); + else + val = clk_readl(mux->reg); + + val >>= mux->shift; val &= mux->mask; if (mux->table) { @@ -93,11 +98,19 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { val = mux->mask << (mux->shift + 16); } else { - val = clk_readl(mux->reg); + if (mux->ll_ops) + val = mux->ll_ops->clk_readl(mux->reg); + else + val = clk_readl(mux->reg); + val &= ~(mux->mask << mux->shift); } val |= index << mux->shift; - clk_writel(val, mux->reg); + + if (mux->ll_ops) + mux->ll_ops->clk_writel(val, mux->reg); + else + clk_writel(val, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); @@ -159,6 +172,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, mux->lock = lock; mux->table = table; mux->hw.init = &init; + mux->ll_ops = &clk_ll_ops_default; clk = clk_register(dev, &mux->hw); @@ -201,6 +215,10 @@ struct clk_hw *clk_register_mux_desc(struct device *dev, struct clk_desc *desc) mux->shift = hw_desc->shift; mux->flags = hw_desc->flags; mux->lock = hw_desc->lock; + mux->ll_ops = hw_desc->ll_ops; + + if (!mux->ll_ops) + mux->ll_ops = &clk_ll_ops_default; if (!desc->ops) { if (mux->flags & CLK_MUX_READ_ONLY) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3923d46..629163c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -408,6 +408,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer + * @ll_ops: low-level ops for accessing the register * @shift: shift to multiplexer bit field * @width: width of mutliplexer bit field * @flags: hardware-specific flags @@ -427,6 +428,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, struct clk_mux { struct clk_hw hw; void __iomem *reg; + struct clk_ll_ops *ll_ops; u32 *table; u32 mask; u8 shift; @@ -438,6 +440,7 @@ struct clk_mux { * struct clk_mux_desc - init descriptor for multiplexer clock * @desc: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer + * @ll_ops: low-level ops for accesing the register * @shift: shift to multiplexer bit field * @width: width of multiplexer bit field * @flags: hardware-specific flags @@ -446,6 +449,7 @@ struct clk_mux { struct clk_mux_desc { struct clk_desc desc; void __iomem *reg; + struct clk_ll_ops *ll_ops; u32 *table; u32 mask; u8 shift;