From patchwork Thu Jan 2 06:52:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lu Jingchang X-Patchwork-Id: 3423961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7535C02DC for ; Thu, 2 Jan 2014 07:49:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8CE0B20131 for ; Thu, 2 Jan 2014 07:49:00 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DBC52012E for ; Thu, 2 Jan 2014 07:48:59 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vyd0u-0006m8-5l; Thu, 02 Jan 2014 07:48:20 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vyd0k-0006XR-QZ; Thu, 02 Jan 2014 07:48:10 +0000 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183] helo=ch1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vyd0f-0006Uh-Bz for linux-arm-kernel@lists.infradead.org; Thu, 02 Jan 2014 07:48:08 +0000 Received: from mail1-ch1-R.bigfish.com (10.43.68.227) by CH1EHSOBE013.bigfish.com (10.43.70.63) with Microsoft SMTP Server id 14.1.225.22; Thu, 2 Jan 2014 07:47:38 +0000 Received: from mail1-ch1 (localhost [127.0.0.1]) by mail1-ch1-R.bigfish.com (Postfix) with ESMTP id 619CF3A0310; Thu, 2 Jan 2014 07:47:38 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail1-ch1 (localhost.localdomain [127.0.0.1]) by mail1-ch1 (MessageSwitch) id 1388648855710936_4782; Thu, 2 Jan 2014 07:47:35 +0000 (UTC) Received: from CH1EHSMHS023.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.230]) by mail1-ch1.bigfish.com (Postfix) with ESMTP id A73F938010A; Thu, 2 Jan 2014 07:47:35 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS023.bigfish.com (10.43.70.23) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 2 Jan 2014 07:47:35 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 2 Jan 2014 07:47:34 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s027lQTU006157; Thu, 2 Jan 2014 00:47:31 -0700 From: Jingchang Lu To: Subject: [PATCHv8 1/2] ARM: dts: vf610: Add eDMA node Date: Thu, 2 Jan 2014 14:52:23 +0800 Message-ID: <1388645544-5596-2-git-send-email-b35083@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1388645544-5596-1-git-send-email-b35083@freescale.com> References: <1388645544-5596-1-git-send-email-b35083@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140102_024805_518844_ECF372FF X-CRM114-Status: GOOD ( 11.38 ) X-Spam-Score: -1.3 (-) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, pawel.moll@arm.com, swarren@wwwdotorg.org, linux-kernel@vger.kernel.org, Jingchang Lu , dan.j.williams@intel.com, shawn.guo@linaro.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UNRESOLVED_TEMPLATE autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Jingchang Lu --- changes in v8: describe dmamux info in edma node to avoid confusion. change eDMA requst source macro definitions. changes in v7: fix dmamux2 and dmamux3 register number. no changes in v2 ~ v6. arch/arm/boot/dts/vf610.dtsi | 31 ++++++ include/dt-bindings/dma/vf610-edma.h | 195 +++++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100644 include/dt-bindings/dma/vf610-edma.h diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index ef8a0ee..9f433b4 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -10,6 +10,7 @@ #include "skeleton.dtsi" #include "vf610-pingrp.h" #include +#include / { aliases { @@ -87,6 +88,21 @@ arm,tag-latency = <2 2 2>; }; + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + interrupts = <0 8 0x04>, + <0 9 0x04>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clocks = <&clks VF610_CLK_DMAMUX0>, + <&clks VF610_CLK_DMAMUX1>; + clock-names = "dmamux0", "dmamux1"; + }; + uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; @@ -262,6 +278,21 @@ reg = <0x40080000 0x80000>; ranges; + edma1: dma-controller@40098000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40098000 0x2000>, + <0x400a1000 0x1000>, + <0x400a2000 0x1000>; + interrupts = <0 10 0x04>, + <0 11 0x04>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clocks = <&clks VF610_CLK_DMAMUX2>, + <&clks VF610_CLK_DMAMUX3>; + clock-names = "dmamux0", "dmamux1"; + }; + uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; diff --git a/include/dt-bindings/dma/vf610-edma.h b/include/dt-bindings/dma/vf610-edma.h new file mode 100644 index 0000000..2c04142 --- /dev/null +++ b/include/dt-bindings/dma/vf610-edma.h @@ -0,0 +1,195 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __DT_BINDINGS_VF610_EDMA_H__ +#define __DT_BINDINGS_VF610_EDMA_H__ + +#define VF610_EDMA_DMAMUX0 0 +#define VF610_EDMA_DMAMUX1 1 + +/* eDMA0 DMAMUX0 group reqeust source(slot) number */ +#define VF610_EDMA0_MUX0_UART0_RX 2 +#define VF610_EDMA0_MUX0_UART0_TX 3 +#define VF610_EDMA0_MUX0_UART1_RX 4 +#define VF610_EDMA0_MUX0_UART1_TX 5 +#define VF610_EDMA0_MUX0_UART2_RX 6 +#define VF610_EDMA0_MUX0_UART2_TX 7 +#define VF610_EDMA0_MUX0_UART3_RX 8 +#define VF610_EDMA0_MUX0_UART3_TX 9 +#define VF610_EDMA0_MUX0_DSPI0_RX 12 +#define VF610_EDMA0_MUX0_DSPI0_TX 13 +#define VF610_EDMA0_MUX0_DSPI1_RX 14 +#define VF610_EDMA0_MUX0_DSPI1_TX 15 +#define VF610_EDMA0_MUX0_SAI0_RX 16 +#define VF610_EDMA0_MUX0_SAI0_TX 17 +#define VF610_EDMA0_MUX0_SAI1_RX 18 +#define VF610_EDMA0_MUX0_SAI1_TX 19 +#define VF610_EDMA0_MUX0_SAI2_RX 20 +#define VF610_EDMA0_MUX0_SAI2_TX 21 +#define VF610_EDMA0_MUX0_PDB 22 +#define VF610_EDMA0_MUX0_FTM0_CH0 24 +#define VF610_EDMA0_MUX0_FTM0_CH1 25 +#define VF610_EDMA0_MUX0_FTM0_CH2 26 +#define VF610_EDMA0_MUX0_FTM0_CH3 27 +#define VF610_EDMA0_MUX0_FTM0_CH4 28 +#define VF610_EDMA0_MUX0_FTM0_CH5 29 +#define VF610_EDMA0_MUX0_FTM0_CH6 30 +#define VF610_EDMA0_MUX0_FTM0_CH7 31 +#define VF610_EDMA0_MUX0_FTM1_CH0 32 +#define VF610_EDMA0_MUX0_FTM1_CH1 33 +#define VF610_EDMA0_MUX0_ADC0 34 +#define VF610_EDMA0_MUX0_QUADSPI0 36 +#define VF610_EDMA0_MUX0_GPIOA 38 +#define VF610_EDMA0_MUX0_GPIOB 39 +#define VF610_EDMA0_MUX0_GPIOC 40 +#define VF610_EDMA0_MUX0_GPIOD 41 +#define VF610_EDMA0_MUX0_GPIOE 42 +#define VF610_EDMA0_MUX0_RLE_RX 45 +#define VF610_EDMA0_MUX0_RLE_TX 46 +#define VF610_EDMA0_MUX0_SPDIF_RX 47 +#define VF610_EDMA0_MUX0_SPDIF_TX 48 +#define VF610_EDMA0_MUX0_I2C0_RX 50 +#define VF610_EDMA0_MUX0_I2C0_TX 51 +#define VF610_EDMA0_MUX0_I2C1_RX 52 +#define VF610_EDMA0_MUX0_I2C1_TX 53 + +/* eDMA DMAMUX1 group request source(slot) number */ +#define VF610_EDMA0_MUX1_UART4_RX 2 +#define VF610_EDMA0_MUX1_UART4_TX 3 +#define VF610_EDMA0_MUX1_UART5_RX 4 +#define VF610_EDMA0_MUX1_UART5_TX 5 +#define VF610_EDMA0_MUX1_SAI3_RX 8 +#define VF610_EDMA0_MUX1_SAI3_TX 9 +#define VF610_EDMA0_MUX1_DSPI2_RX 10 +#define VF610_EDMA0_MUX1_DSPI2_TX 11 +#define VF610_EDMA0_MUX1_DSPI3_RX 12 +#define VF610_EDMA0_MUX1_DSPI3_TX 13 +#define VF610_EDMA0_MUX1_FTM2_CH0 16 +#define VF610_EDMA0_MUX1_FTM2_CH1 17 +#define VF610_EDMA0_MUX1_FTM3_CH0 18 +#define VF610_EDMA0_MUX1_FTM3_CH1 19 +#define VF610_EDMA0_MUX1_FTM3_CH2 20 +#define VF610_EDMA0_MUX1_FTM3_CH3 21 +#define VF610_EDMA0_MUX1_FTM3_CH4 22 +#define VF610_EDMA0_MUX1_FTM3_CH5 24 +#define VF610_EDMA0_MUX1_FTM3_CH6 25 +#define VF610_EDMA0_MUX1_FTM3_CH7 26 +#define VF610_EDMA0_MUX1_QUADSPI1 27 +#define VF610_EDMA0_MUX1_DAC0 32 +#define VF610_EDMA0_MUX1_DAC1 33 +#define VF610_EDMA0_MUX1_ESAI_BIFIFO_TX 34 +#define VF610_EDMA0_MUX1_ESAI_BIFIFO_RX 35 +#define VF610_EDMA0_MUX1_I2C2_RX 36 +#define VF610_EDMA0_MUX1_I2C2_TX 37 +#define VF610_EDMA0_MUX1_I2C3_RX 38 +#define VF610_EDMA0_MUX1_I2C3_TX 39 +#define VF610_EDMA0_MUX1_ASRC0_TX 40 +#define VF610_EDMA0_MUX1_ASRC0_RX 41 +#define VF610_EDMA0_MUX1_ASRC1_TX 42 +#define VF610_EDMA0_MUX1_ASRC1_RX 43 +#define VF610_EDMA0_MUX1_TIMER0 44 +#define VF610_EDMA0_MUX1_TIMER1 45 +#define VF610_EDMA0_MUX1_TIMER2 46 +#define VF610_EDMA0_MUX1_TIMER3 47 +#define VF610_EDMA0_MUX1_TIMER4 48 +#define VF610_EDMA0_MUX1_TIMER5 49 +#define VF610_EDMA0_MUX1_TIMER6 50 +#define VF610_EDMA0_MUX1_TIMER7 51 + +/* eDMA1 DMAMUX0 request source(slot) number */ +#define VF610_EDMA1_MUX0_UART4_RX 2 +#define VF610_EDMA1_MUX0_UART4_TX 3 +#define VF610_EDMA1_MUX0_UART5_RX 4 +#define VF610_EDMA1_MUX0_UART5_TX 5 +#define VF610_EDMA1_MUX0_SAI3_RX 8 +#define VF610_EDMA1_MUX0_SAI3_TX 9 +#define VF610_EDMA1_MUX0_DSPI2_RX 10 +#define VF610_EDMA1_MUX0_DSPI2_TX 11 +#define VF610_EDMA1_MUX0_DSPI3_RX 12 +#define VF610_EDMA1_MUX0_DSPI3_TX 13 +#define VF610_EDMA1_MUX0_FTM2_CH0 16 +#define VF610_EDMA1_MUX0_FTM2_CH1 17 +#define VF610_EDMA1_MUX0_FTM3_CH0 18 +#define VF610_EDMA1_MUX0_FTM3_CH1 19 +#define VF610_EDMA1_MUX0_FTM3_CH2 20 +#define VF610_EDMA1_MUX0_FTM3_CH3 21 +#define VF610_EDMA1_MUX0_FTM3_CH4 22 +#define VF610_EDMA1_MUX0_FTM3_CH5 24 +#define VF610_EDMA1_MUX0_FTM3_CH6 25 +#define VF610_EDMA1_MUX0_FTM3_CH7 26 +#define VF610_EDMA1_MUX0_QUADSPI1 27 +#define VF610_EDMA1_MUX0_DAC0 32 +#define VF610_EDMA1_MUX0_DAC1 33 +#define VF610_EDMA1_MUX0_ESAI_BIFIFO_TX 34 +#define VF610_EDMA1_MUX0_ESAI_BIFIFO_RX 35 +#define VF610_EDMA1_MUX0_I2C2_RX 36 +#define VF610_EDMA1_MUX0_I2C2_TX 37 +#define VF610_EDMA1_MUX0_I2C3_RX 38 +#define VF610_EDMA1_MUX0_I2C3_TX 39 +#define VF610_EDMA1_MUX0_ASRC0_TX 40 +#define VF610_EDMA1_MUX0_ASRC0_RX 41 +#define VF610_EDMA1_MUX0_ASRC1_TX 42 +#define VF610_EDMA1_MUX0_ASRC1_RX 43 +#define VF610_EDMA1_MUX0_TIMER0 44 +#define VF610_EDMA1_MUX0_TIMER1 45 +#define VF610_EDMA1_MUX0_TIMER2 46 +#define VF610_EDMA1_MUX0_TIMER3 47 +#define VF610_EDMA1_MUX0_TIMER4 48 +#define VF610_EDMA1_MUX0_TIMER5 49 +#define VF610_EDMA1_MUX0_TIMER6 50 +#define VF610_EDMA1_MUX0_TIMER7 51 + +/* eDMA1 DMAMUX1 group reqeust source(slot) number */ +#define VF610_EDMA1_MUX1_UART0_RX 2 +#define VF610_EDMA1_MUX1_UART0_TX 3 +#define VF610_EDMA1_MUX1_UART1_RX 4 +#define VF610_EDMA1_MUX1_UART1_TX 5 +#define VF610_EDMA1_MUX1_UART2_RX 6 +#define VF610_EDMA1_MUX1_UART2_TX 7 +#define VF610_EDMA1_MUX1_UART3_RX 8 +#define VF610_EDMA1_MUX1_UART3_TX 9 +#define VF610_EDMA1_MUX1_DSPI0_RX 12 +#define VF610_EDMA1_MUX1_DSPI0_TX 13 +#define VF610_EDMA1_MUX1_DSPI1_RX 14 +#define VF610_EDMA1_MUX1_DSPI1_TX 15 +#define VF610_EDMA1_MUX1_SAI0_RX 16 +#define VF610_EDMA1_MUX1_SAI0_TX 17 +#define VF610_EDMA1_MUX1_SAI1_RX 18 +#define VF610_EDMA1_MUX1_SAI1_TX 19 +#define VF610_EDMA1_MUX1_SAI2_RX 20 +#define VF610_EDMA1_MUX1_SAI2_TX 21 +#define VF610_EDMA1_MUX1_PDB 22 +#define VF610_EDMA1_MUX1_FTM0_CH0 24 +#define VF610_EDMA1_MUX1_FTM0_CH1 25 +#define VF610_EDMA1_MUX1_FTM0_CH2 26 +#define VF610_EDMA1_MUX1_FTM0_CH3 27 +#define VF610_EDMA1_MUX1_FTM0_CH4 28 +#define VF610_EDMA1_MUX1_FTM0_CH5 29 +#define VF610_EDMA1_MUX1_FTM0_CH6 30 +#define VF610_EDMA1_MUX1_FTM0_CH7 31 +#define VF610_EDMA1_MUX1_FTM1_CH0 32 +#define VF610_EDMA1_MUX1_FTM1_CH1 33 +#define VF610_EDMA1_MUX1_ADC0 34 +#define VF610_EDMA1_MUX1_QUADSPI0 36 +#define VF610_EDMA1_MUX1_GPIOA 38 +#define VF610_EDMA1_MUX1_GPIOB 39 +#define VF610_EDMA1_MUX1_GPIOC 40 +#define VF610_EDMA1_MUX1_GPIOD 41 +#define VF610_EDMA1_MUX1_GPIOE 42 +#define VF610_EDMA1_MUX1_RLE_RX 45 +#define VF610_EDMA1_MUX1_RLE_TX 46 +#define VF610_EDMA1_MUX1_SPDIF_RX 47 +#define VF610_EDMA1_MUX1_SPDIF_TX 48 +#define VF610_EDMA1_MUX1_I2C0_RX 50 +#define VF610_EDMA1_MUX1_I2C0_TX 51 +#define VF610_EDMA1_MUX1_I2C1_RX 52 +#define VF610_EDMA1_MUX1_I2C1_TX 53 + +#endif