From patchwork Sun Jan 12 11:00:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 3471481 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 369499F2ED for ; Sun, 12 Jan 2014 11:03:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3056E20122 for ; Sun, 12 Jan 2014 11:03:57 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 344B620121 for ; Sun, 12 Jan 2014 11:03:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2Io5-0000fq-3v; Sun, 12 Jan 2014 11:02:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2Ina-0007h6-UY; Sun, 12 Jan 2014 11:01:46 +0000 Received: from juliette.telenet-ops.be ([195.130.137.74]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2Imz-0007cy-JW for linux-arm-kernel@lists.infradead.org; Sun, 12 Jan 2014 11:01:16 +0000 Received: from ayla.of.borg ([84.193.72.141]) by juliette.telenet-ops.be with bizsmtp id Cz0h1n01432ts5g06z0h1f; Sun, 12 Jan 2014 12:00:46 +0100 Received: from geert by ayla.of.borg with local (Exim 4.76) (envelope-from ) id 1W2ImX-0000kf-On; Sun, 12 Jan 2014 12:00:41 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , Laurent Pinchart Subject: [PATCH V2 1/4] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups Date: Sun, 12 Jan 2014 12:00:30 +0100 Message-Id: <1389524433-2823-2-git-send-email-geert@linux-m68k.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389524433-2823-1-git-send-email-geert@linux-m68k.org> References: <1389524433-2823-1-git-send-email-geert@linux-m68k.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140112_060110_241585_3D215A9F X-CRM114-Status: GOOD ( 10.53 ) X-Spam-Score: -1.9 (-) Cc: Geert Uytterhoeven , linux-spi@vger.kernel.org, "Cc: Linus Walleij" , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven Cc: Cc: Linus Walleij Acked-by: Laurent Pinchart --- V2: - Split in 2 sets of 3 pin groups drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 654bef369ab8..0ac8264440df 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2135,6 +2135,53 @@ static const unsigned int msiof2_tx_pins[] = { static const unsigned int msiof2_tx_mux[] = { MSIOF2_TXD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 8), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; + +static const unsigned int qspi_ctrl_b_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi_ctrl_b_mux[] = { + SPCLK_B_MARK, SSL_B_MARK, +}; +static const unsigned int qspi_data2_b_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), +}; +static const unsigned int qspi_data2_b_mux[] = { + MOSI_IO0_B_MARK, MISO_IO1_B_MARK, +}; +static const unsigned int qspi_data4_b_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), + RCAR_GP_PIN(6, 4), +}; +static const unsigned int qspi_data4_b_mux[] = { + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK, + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -2877,6 +2924,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof2_ss2), SH_PFC_PIN_GROUP(msiof2_rx), SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -3074,6 +3127,15 @@ static const char * const msiof2_groups[] = { "msiof2_tx", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", + "qspi_ctrl_b", + "qspi_data2_b", + "qspi_data4_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_data_b", @@ -3230,6 +3292,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2),