From patchwork Fri Jan 17 15:03:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 3506341 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 730C0C02DC for ; Fri, 17 Jan 2014 17:06:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 526982017D for ; Fri, 17 Jan 2014 17:06:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FC9F200E9 for ; Fri, 17 Jan 2014 17:06:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Azj-0007fO-H2; Fri, 17 Jan 2014 15:06:06 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Az1-0003c8-T7; Fri, 17 Jan 2014 15:05:19 +0000 Received: from mail-lb0-x232.google.com ([2a00:1450:4010:c04::232]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4AyF-0003QZ-94 for linux-arm-kernel@lists.infradead.org; Fri, 17 Jan 2014 15:04:34 +0000 Received: by mail-lb0-f178.google.com with SMTP id u14so3073635lbd.9 for ; Fri, 17 Jan 2014 07:04:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4IilLQkQSKhEFKDi+mjR4gYOeCZpnLpa5stZHbjEHgo=; b=MCDo+2YJLOpmkPYdK8cQTb7vngBtv7UJNd5S4CvjLeRKCVkWiast5Uy0yZJ01t/c6M SyuavpIBHaPMNB3Q/TFZCM0WCOPKrwbvwOifxP7RkKG2O1vgSlQzPMTvjCeCIDdRfqEV CRVh1sqkrmm7qtk4KNQ39L51k+lvk1bx4Ti2tgd6cgahMO4MTw9J95bZYnQ6/TBwKu8f tIQ6rTFi3gMTIdc7qqlEoEcfQprHDvigo7wFiD/rtPh4gh0yeeZZwA2RlQoxa2iGdMz/ dMRo72kzOLL94t+ijvclhU7KfB8qZqkVb6kDWwBW1pQ7QoBguQbK/uYJqAx9YX7s6ZR4 UyKw== X-Received: by 10.152.20.201 with SMTP id p9mr427188lae.69.1389971048591; Fri, 17 Jan 2014 07:04:08 -0800 (PST) Received: from Ildjarn.ath.cx (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id ld10sm8396252lab.8.2014.01.17.07.04.06 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 17 Jan 2014 07:04:07 -0800 (PST) From: Jonas Jensen To: mturquette@linaro.org Subject: [PATCH v9] clk: add MOXA ART SoCs clock driver Date: Fri, 17 Jan 2014 16:03:55 +0100 Message-Id: <1389971035-17781-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1386602163-28479-1-git-send-email-jonas.jensen@gmail.com> References: <1386602163-28479-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140117_100431_704227_F28E23EE X-CRM114-Status: GOOD ( 14.12 ) X-Spam-Score: -2.0 (--) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, adam.jaremko@gmail.com, linux-kernel@vger.kernel.org, tomasz.figa@gmail.com, arm@kernel.org, sylvester.nawrocki@gmail.com, Jonas Jensen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds MOXA ART SoCs clock driver support. Signed-off-by: Jonas Jensen --- Notes: Changes since v8: 1. rebase drivers/clk/Makefile to next-20140117 DT bindings document: 2. use two separate sections describing PLL/APB 3. update example Applies to next-20140117 .../bindings/clock/moxa,moxart-clock.txt | 48 +++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-moxart.c | 112 +++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt create mode 100644 drivers/clk/clk-moxart.c diff --git a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt new file mode 100644 index 0000000..242e3fc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt @@ -0,0 +1,48 @@ +Device Tree Clock bindings for arch-moxart + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +MOXA ART SoCs allow to determine PLL output and APB frequencies +by reading registers holding multiplier and divisor information. + + +PLL: + +Required properties: +- compatible : Must be "moxa,moxart-pll-clock" +- #clock-cells : Should be 0 +- reg : Should contain registers location and length +- clocks : Should contain phandle to parent clock + +Optional properties: +- clock-output-names : Should contain clock name + + +APB: + +Required properties: +- compatible : Must be "moxa,moxart-apb-clock" +- #clock-cells : Should be 0 +- reg : Should contain registers location and length +- clocks : Should contain phandle to parent clock + +Optional properties: +- clock-output-names : Should contain clock name + + +For example: + + clk_pll: clk_pll@98100000 { + compatible = "moxa,moxart-pll-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + }; + + clk_apb: clk_apb@98100000 { + compatible = "moxa,moxart-apb-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&clk_pll>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0c16e9c..ed5d58d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o # SoCs specific obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c new file mode 100644 index 0000000..f0436a3 --- /dev/null +++ b/drivers/clk/clk-moxart.c @@ -0,0 +1,112 @@ +/* + * MOXA ART SoCs clock driver. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +void __init moxart_of_pll_clk_init(struct device_node *node) +{ + static void __iomem *base; + struct clk *clk, *ref_clk; + unsigned long rate; + unsigned int mul; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + + mul = readl(base + 0x30) >> 3 & 0x3f; + iounmap(base); + + ref_clk = of_clk_get(node, 0); + if (IS_ERR(ref_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = mul * clk_get_rate(ref_clk); + + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); + if (IS_ERR(clk)) { + pr_err("%s: clk_register_fixed_rate failed\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", + moxart_of_pll_clk_init); + +void __init moxart_of_apb_clk_init(struct device_node *node) +{ + static void __iomem *base; + struct clk *clk, *pll_clk; + unsigned long rate; + unsigned int div, val; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + + val = readl(base + 0xc) >> 4 & 0x7; + iounmap(base); + + switch (val) { + case 1: + div = 3; + break; + case 2: + div = 4; + break; + case 3: + div = 6; + break; + case 4: + div = 8; + break; + default: + div = 2; + break; + } + + pll_clk = of_clk_get(node, 0); + if (IS_ERR(pll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = clk_get_rate(pll_clk) / (div * 2); + + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); + if (IS_ERR(clk)) { + pr_err("%s: clk_register_fixed_rate failed\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock", + moxart_of_apb_clk_init);