From patchwork Sat Jan 18 12:10:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 3508311 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E666C02DC for ; Sat, 18 Jan 2014 12:53:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5067E2017B for ; Sat, 18 Jan 2014 12:53:43 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32F4E20158 for ; Sat, 18 Jan 2014 12:53:42 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4VP6-0007wg-GW; Sat, 18 Jan 2014 12:53:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4UlD-0003kF-8T; Sat, 18 Jan 2014 12:12:23 +0000 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Uky-0003iZ-Nh for linux-arm-kernel@lists.infradead.org; Sat, 18 Jan 2014 12:12:10 +0000 Received: by mail-pa0-f45.google.com with SMTP id lf10so2939808pab.4 for ; Sat, 18 Jan 2014 04:11:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OaMVVvx1VL+Ab5cGkEMYY9sRTMquKCRlFULBKNt9miM=; b=Qg7LO68hQIBXNbSb6rvDv9rNlMfR3Wng18/yt/HGjO+Sld13KQoNowuvsGsED3xLHM Vqlqz/ts/N+wiyK/05la+haqI+COS+RbuT7J2bfJ+EeEINhp/QW96xBSHzmASXgOQCc9 drQI3tHMs5cuHanQZpBAL5U2X8ST4Zm8G3KcOXOL/IodyiGnMxbUITyYOen7MfP8yYPp iA5i+BMo+ggLKuRPiMAyRnr3mtjIpFRUS+LmMZtXMhJ7U/8Xj17CiRDcCRJillyvhAIi daNPRdpIh66OiQEF+Tid0jt0wFA9/lt8Ly/hK06JNbm08SEP8ViHylp3tWtry9Ru2/4s moCw== X-Received: by 10.67.14.69 with SMTP id fe5mr2513281pad.120.1390047106515; Sat, 18 Jan 2014 04:11:46 -0800 (PST) Received: from user-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id gn5sm29858876pbc.29.2014.01.18.04.11.41 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 18 Jan 2014 04:11:44 -0800 (PST) From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/7] cpufreq: cpufreq-cpu0: allow optional safe voltage during frequency transitions Date: Sat, 18 Jan 2014 17:40:51 +0530 Message-Id: <1390047057-2239-2-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> References: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140118_071208_958532_1D2C6754 X-CRM114-Status: GOOD ( 19.96 ) X-Spam-Score: -2.0 (--) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, viresh.kumar@linaro.org, t.figa@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham On some platforms such as the Samsung Exynos, changing the frequency of the CPU clock requires changing the frequency of the PLL that is supplying the CPU clock. To change the frequency of the PLL, the CPU clock is temporarily reparented to another parent clock. The clock frequency of this temporary parent clock could be much higher than the clock frequency of the PLL at the time of reparenting. Due to the temporary increase in the CPU clock speed, the CPU (and any other components in the CPU clock domain such as dividers, mux, etc.) have to to be operated at a higher voltage level, called the safe voltage level. This patch adds optional support to temporarily switch to a safe voltage level during CPU frequency transitions. Cc: Shawn Guo Signed-off-by: Thomas Abraham Reviewed-by: Lukasz Majewski Acked-by: Shawn Guo --- .../devicetree/bindings/cpufreq/cpufreq-cpu0.txt | 7 ++++ drivers/cpufreq/cpufreq-cpu0.c | 37 +++++++++++++++++-- 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt index f055515..37453ab 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt @@ -19,6 +19,12 @@ Optional properties: - cooling-min-level: - cooling-max-level: Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. +- safe-opp: Certain platforms require that during a opp transition, + a system should not go below a particular opp level. For such systems, + this property specifies the minimum opp to be maintained during the + opp transitions. The safe-opp value is a tuple with first element + representing the safe frequency and the second element representing the + safe voltage. Examples: @@ -36,6 +42,7 @@ cpus { 396000 950000 198000 850000 >; + safe-opp = <396000 950000> clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; cooling-min-level = <0>; diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c index 0c12ffc..075d3d1 100644 --- a/drivers/cpufreq/cpufreq-cpu0.c +++ b/drivers/cpufreq/cpufreq-cpu0.c @@ -27,6 +27,8 @@ static unsigned int transition_latency; static unsigned int voltage_tolerance; /* in percentage */ +static unsigned long safe_frequency; +static unsigned long safe_voltage; static struct device *cpu_dev; static struct clk *cpu_clk; @@ -64,17 +66,30 @@ static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index) volt_old = regulator_get_voltage(cpu_reg); } - pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", + pr_debug("\n\n%u MHz, %ld mV --> %u MHz, %ld mV\n", old_freq / 1000, volt_old ? volt_old / 1000 : -1, new_freq / 1000, volt ? volt / 1000 : -1); /* scaling up? scale voltage before frequency */ - if (!IS_ERR(cpu_reg) && new_freq > old_freq) { + if (!IS_ERR(cpu_reg) && new_freq > old_freq && + new_freq >= safe_frequency) { ret = regulator_set_voltage_tol(cpu_reg, volt, tol); if (ret) { pr_err("failed to scale voltage up: %d\n", ret); return ret; } + } else if (!IS_ERR(cpu_reg) && old_freq < safe_frequency) { + /* + * the scaled up voltage level for the new_freq is lower + * than the safe voltage level. so set safe_voltage + * as the intermediate voltage level and revert it + * back after the frequency has been changed. + */ + ret = regulator_set_voltage_tol(cpu_reg, safe_voltage, tol); + if (ret) { + pr_err("failed to set safe voltage: %d\n", ret); + return ret; + } } ret = clk_set_rate(cpu_clk, freq_exact); @@ -86,7 +101,8 @@ static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index) } /* scaling down? scale voltage after frequency */ - if (!IS_ERR(cpu_reg) && new_freq < old_freq) { + if (!IS_ERR(cpu_reg) && + (new_freq < old_freq || new_freq < safe_frequency)) { ret = regulator_set_voltage_tol(cpu_reg, volt, tol); if (ret) { pr_err("failed to scale voltage down: %d\n", ret); @@ -116,6 +132,8 @@ static struct cpufreq_driver cpu0_cpufreq_driver = { static int cpu0_cpufreq_probe(struct platform_device *pdev) { + const struct property *prop; + struct dev_pm_opp *opp; struct device_node *np; int ret; @@ -165,13 +183,24 @@ static int cpu0_cpufreq_probe(struct platform_device *pdev) goto out_put_node; } + prop = of_find_property(np, "safe-opp", NULL); + if (prop) { + if (prop->value && (prop->length / sizeof(u32)) == 2) { + const __be32 *val; + val = prop->value; + safe_frequency = be32_to_cpup(val++); + safe_voltage = be32_to_cpup(val); + } else { + pr_err("invalid safe-opp level specified\n"); + } + } + of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); if (of_property_read_u32(np, "clock-latency", &transition_latency)) transition_latency = CPUFREQ_ETERNAL; if (!IS_ERR(cpu_reg)) { - struct dev_pm_opp *opp; unsigned long min_uV, max_uV; int i;