From patchwork Mon Feb 3 14:28:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas KANDAGATLA X-Patchwork-Id: 3569721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7BCAF9F2F5 for ; Mon, 3 Feb 2014 14:38:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7042A201D5 for ; Mon, 3 Feb 2014 14:38:40 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18F3D201D3 for ; Mon, 3 Feb 2014 14:38:39 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAKdh-0007eU-St; Mon, 03 Feb 2014 14:36:47 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAKdO-0002P6-1e; Mon, 03 Feb 2014 14:36:26 +0000 Received: from eu1sys200aog106.obsmtp.com ([207.126.144.121]) by merlin.infradead.org with smtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WAKcv-0002J9-Kt for linux-arm-kernel@lists.infradead.org; Mon, 03 Feb 2014 14:36:00 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob106.postini.com ([207.126.147.11]) with SMTP ID DSNKUu+pLLzp+TYFQB5G0rmc/3BSrkDmAmwG@postini.com; Mon, 03 Feb 2014 14:35:57 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CCAA2132; Mon, 3 Feb 2014 14:34:34 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6A92F164CB; Mon, 3 Feb 2014 14:35:21 +0000 (GMT) Received: from localhost (10.65.51.147) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.123.3; Mon, 3 Feb 2014 15:35:23 +0100 From: To: Subject: [PATCH v2 5/6] drivers: reset: stih416: add softreset controller Date: Mon, 3 Feb 2014 14:28:57 +0000 Message-ID: <1391437737-12143-1-git-send-email-srinivas.kandagatla@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com> References: <1391437665-11913-1-git-send-email-srinivas.kandagatla@st.com> MIME-Version: 1.0 X-Originating-IP: [10.65.51.147] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140203_093558_040026_43029A43 X-CRM114-Status: GOOD ( 16.95 ) X-Spam-Score: -4.2 (----) Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , Rob Landley , Pawel Moll , Ian Campbell , Olof Johansson , Srinivas Kandagatla , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, stephen.gallimore@st.com, Stuart Menefy , Rob Herring , Arnd Bergmann , Philipp Zabel , Kumar Gala , Grant Likely , kernel@stlinux.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds softreset controller for STiH416 SOC, soft reset controller is based on system configuration registers which are mapped via regmap. This reset controller does not have any feedback or acknowledgement. With this patch a new device "st,stih416-softreset" is registered with system configuration registers based reset controller that controls the softreset state of the hardware such as Ethernet, IRB. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/stih416.dtsi | 5 ++ drivers/reset/sti/reset-stih416.c | 64 ++++++++++++++++++++ .../dt-bindings/reset-controller/stih416-resets.h | 29 +++++++++ 3 files changed, 98 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index e5bec66..788ba5b 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -33,6 +33,11 @@ compatible = "st,stih416-powerdown"; }; + softreset: softreset-controller { + #reset-cells = <1>; + compatible = "st,stih416-softreset"; + }; + syscfg_sbc:sbc-syscfg@fe600000{ compatible = "st,stih416-sbc-syscfg", "syscon"; reg = <0xfe600000 0x1000>; diff --git a/drivers/reset/sti/reset-stih416.c b/drivers/reset/sti/reset-stih416.c index 0becfc5..fe3bf02 100644 --- a/drivers/reset/sti/reset-stih416.c +++ b/drivers/reset/sti/reset-stih416.c @@ -24,6 +24,7 @@ static const char stih416_front[] = "st,stih416-front-syscfg"; static const char stih416_rear[] = "st,stih416-rear-syscfg"; static const char stih416_sbc[] = "st,stih416-sbc-syscfg"; static const char stih416_lpm[] = "st,stih416-lpm-syscfg"; +static const char stih416_cpu[] = "st,stih416-cpu-syscfg"; #define STIH416_PDN_FRONT(_bit) \ _SYSCFG_RST_CH(stih416_front, SYSCFG_1500, _bit, SYSSTAT_1578, _bit) @@ -37,6 +38,29 @@ static const char stih416_lpm[] = "st,stih416-lpm-syscfg"; #define SYSCFG_2525 0x834 /* Powerdown request USB/SATA/PCIe */ #define SYSSTAT_2583 0x91c /* Powerdown status USB/SATA/PCIe */ +#define SYSCFG_2552 0x8A0 /* Reset Generator control 0 */ +#define SYSCFG_1539 0x86c /* Softreset Ethernet 0 */ +#define SYSCFG_510 0x7f8 /* Softreset Ethernet 1 */ +#define LPM_SYSCFG_1 0x4 /* Softreset IRB */ +#define SYSCFG_2553 0x8a4 /* Softreset SATA0/1, PCIE0/1 */ +#define SYSCFG_7563 0x8cc /* MPE softresets 0 */ +#define SYSCFG_7564 0x8d0 /* MPE softresets 1 */ + +#define STIH416_SRST_CPU(_reg, _bit) \ + _SYSCFG_RST_CH_NO_ACK(stih416_cpu, _reg, _bit) + +#define STIH416_SRST_FRONT(_reg, _bit) \ + _SYSCFG_RST_CH_NO_ACK(stih416_front, _reg, _bit) + +#define STIH416_SRST_REAR(_reg, _bit) \ + _SYSCFG_RST_CH_NO_ACK(stih416_rear, _reg, _bit) + +#define STIH416_SRST_LPM(_reg, _bit) \ + _SYSCFG_RST_CH_NO_ACK(stih416_lpm, _reg, _bit) + +#define STIH416_SRST_SBC(_reg, _bit) \ + _SYSCFG_RST_CH_NO_ACK(stih416_sbc, _reg, _bit) + static const struct syscfg_reset_channel_data stih416_powerdowns[] = { [STIH416_EMISS_POWERDOWN] = STIH416_PDN_FRONT(0), [STIH416_NAND_POWERDOWN] = STIH416_PDN_FRONT(1), @@ -51,15 +75,55 @@ static const struct syscfg_reset_channel_data stih416_powerdowns[] = { [STIH416_PCIE1_POWERDOWN] = STIH416_PDN_REAR(5, 8), }; +static const struct syscfg_reset_channel_data stih416_softresets[] = { + [STIH416_ETH0_SOFTRESET] = STIH416_SRST_FRONT(SYSCFG_1539, 0), + [STIH416_ETH1_SOFTRESET] = STIH416_SRST_SBC(SYSCFG_510, 0), + [STIH416_IRB_SOFTRESET] = STIH416_SRST_LPM(LPM_SYSCFG_1, 6), + [STIH416_USB0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 9), + [STIH416_USB1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 10), + [STIH416_USB2_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 11), + [STIH416_USB3_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 28), + [STIH416_SATA0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 7), + [STIH416_SATA1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 3), + [STIH416_PCIE0_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 15), + [STIH416_PCIE1_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 2), + [STIH416_AUD_DAC_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 14), + [STIH416_HDTVOUT_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 5), + [STIH416_VTAC_M_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 25), + [STIH416_VTAC_A_RX_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2552, 26), + [STIH416_SYNC_HD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 5), + [STIH416_SYNC_SD_SOFTRESET] = STIH416_SRST_REAR(SYSCFG_2553, 6), + [STIH416_BLITTER_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 10), + [STIH416_GPU_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 11), + [STIH416_VTAC_M_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 18), + [STIH416_VTAC_A_TX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 19), + [STIH416_VTG_AUX_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 21), + [STIH416_JPEG_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7563, 23), + [STIH416_HVA_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 2), + [STIH416_COMPO_M_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 3), + [STIH416_COMPO_A_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 4), + [STIH416_VP8_DEC_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 10), + [STIH416_VTG_MAIN_SOFTRESET] = STIH416_SRST_CPU(SYSCFG_7564, 16), +}; + static struct syscfg_reset_controller_data stih416_powerdown_controller = { .wait_for_ack = true, .nr_channels = ARRAY_SIZE(stih416_powerdowns), .channels = stih416_powerdowns, }; +static struct syscfg_reset_controller_data stih416_softreset_controller = { + .wait_for_ack = false, + .active_low = true, + .nr_channels = ARRAY_SIZE(stih416_softresets), + .channels = stih416_softresets, +}; + static struct of_device_id stih416_reset_match[] = { { .compatible = "st,stih416-powerdown", .data = &stih416_powerdown_controller, }, + { .compatible = "st,stih416-softreset", + .data = &stih416_softreset_controller, }, {}, }; diff --git a/include/dt-bindings/reset-controller/stih416-resets.h b/include/dt-bindings/reset-controller/stih416-resets.h index d7da55f..2127743 100644 --- a/include/dt-bindings/reset-controller/stih416-resets.h +++ b/include/dt-bindings/reset-controller/stih416-resets.h @@ -18,4 +18,33 @@ #define STIH416_PCIE0_POWERDOWN 9 #define STIH416_PCIE1_POWERDOWN 10 +#define STIH416_ETH0_SOFTRESET 0 +#define STIH416_ETH1_SOFTRESET 1 +#define STIH416_IRB_SOFTRESET 2 +#define STIH416_USB0_SOFTRESET 3 +#define STIH416_USB1_SOFTRESET 4 +#define STIH416_USB2_SOFTRESET 5 +#define STIH416_USB3_SOFTRESET 6 +#define STIH416_SATA0_SOFTRESET 7 +#define STIH416_SATA1_SOFTRESET 8 +#define STIH416_PCIE0_SOFTRESET 9 +#define STIH416_PCIE1_SOFTRESET 10 +#define STIH416_AUD_DAC_SOFTRESET 11 +#define STIH416_HDTVOUT_SOFTRESET 12 +#define STIH416_VTAC_M_RX_SOFTRESET 13 +#define STIH416_VTAC_A_RX_SOFTRESET 14 +#define STIH416_SYNC_HD_SOFTRESET 15 +#define STIH416_SYNC_SD_SOFTRESET 16 +#define STIH416_BLITTER_SOFTRESET 17 +#define STIH416_GPU_SOFTRESET 18 +#define STIH416_VTAC_M_TX_SOFTRESET 19 +#define STIH416_VTAC_A_TX_SOFTRESET 20 +#define STIH416_VTG_AUX_SOFTRESET 21 +#define STIH416_JPEG_DEC_SOFTRESET 22 +#define STIH416_HVA_SOFTRESET 23 +#define STIH416_COMPO_M_SOFTRESET 24 +#define STIH416_COMPO_A_SOFTRESET 25 +#define STIH416_VP8_DEC_SOFTRESET 26 +#define STIH416_VTG_MAIN_SOFTRESET 27 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */